Patents by Inventor Jiro Yoshida

Jiro Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5545612
    Abstract: A superconductor element includes a first layer of an oxide superconductor, a second layer of an insulator, semiconductor, or metal, and an interlayer interposed between the first and second layers and formed of AgO.sub.x (where in 0<.times.< 1/2) .
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: August 13, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Mizushima, Jiro Yoshida, Koh-ichi Kubo
  • Patent number: 5378875
    Abstract: A microwave oven has only a microwave sensor or both microwave sensor and temperature sensor. The microwave sensor has a wave absorber to generate heat through absorption of microwave energy and a thermistor to detect temperature of this wave absorber. The temperature sensor has a thermistor to detect the ambient temperature around the wave absorber. A controller determines a value of microwave power on the basis of the output of the microwave sensor or each output of the microwave sensor and temperature sensor. The microwave oven can accurately detect microwave power without being influenced by variation of ambient temperature around the microwave sensor.
    Type: Grant
    Filed: December 11, 1992
    Date of Patent: January 3, 1995
    Assignee: Mitsubishi Materials Corporation
    Inventors: Masahiro Hirama, Masami Koshimura, Sakae Mori, Jiro Yoshida
  • Patent number: 4768074
    Abstract: A heterojunction bipolar transistor comprises a base region of a first conductivity type formed of a first kind of semiconductor material, an emitter region of a second conductivity type formed of a second kind of semiconductor material which has a band gap greater than that of the first kind of semiconductor material and a smaller electron affinity, a transition region formed between the base region and the emitter region, and a collector region formed adjacent to the base region. The transition region is formed of a plurality of semiconductor layers such that band gaps sequentially increase in a stepped fashion from the semiconductor layer adjacent to the base region toward the semiconductor layer adjacent to the emitter region. The transition region is formed of a semiconductor material having an intermediate composition between the composition of the first kind of semiconductor material and that of the second kind of semiconductor material.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: August 30, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jiro Yoshida, Makoto Azuma
  • Patent number: 4739379
    Abstract: A heterojunction bipolar integrated circuit is disclosed which uses a heterojunction bipolar transistor with a heterojunction between an emitter region and a base region. In this transistor, a pn junction between the base region and the emitter region has a greater area than a pn junction between the base region and a collector region. A plurality of such heterojunction bipolar transistors are isolated on a substrate to perform logic operations in an unsaturated region.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: April 19, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junko Akagi, Jiro Yoshida, Makoto Azuma
  • Patent number: 4593305
    Abstract: A heterostructure bipolar transistor has an emitter layer, a base layer and a collector layer, the emitter layer being formed of a semiconductor material whose energy gap is wider than that of the base layer, so that a heterojunction is formed between the emitter layer and the base layer. One of the emitter layer and the base layer has first and second layers which are sequentially formed, and the first layer constituting the heterojunction has a lower impurity concentration than that of the second layer. When the impurity concentration and the thickness of the first layer are defined as N.sub.1 and W.sub.1, respectively, the following relation is satisfied:N.sub.1 W.sub.1.sup.2 .ltoreq.(2.epsilon..sub.s .epsilon..sub.0 /q)V.sub.biwhereq: the absolute value of electron charge(=1.6.times.10.sup.-19 Coulombs),.epsilon..sub.0 : the free space permittivity(=8.86.times.10.sup.-14 farads/cm),.epsilon..sub.s1 : the dielectric constant of the first layer, andV.sub.bi : the built-in potential at the heterojunction.
    Type: Grant
    Filed: May 8, 1984
    Date of Patent: June 3, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mamoru Kurata, Jiro Yoshida