Patents by Inventor Jitendra Prabhakar Harshey
Jitendra Prabhakar Harshey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11539351Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the fType: GrantFiled: June 17, 2021Date of Patent: December 27, 2022Assignee: NXP B.V.Inventors: Henricus Cornelis Johannes Büthker, Jitendra Prabhakar Harshey
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Publication number: 20220407503Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the fType: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Inventors: Henricus Cornelis Johannes Büthker, Jitendra Prabhakar Harshey
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Publication number: 20210211055Abstract: A DC-DC converter operates in a burst mode having at least one charge cycle with a charging phase followed by a discharging phase. A charging phase is terminated when an inductor current flowing through an inductance connected to the DC-DC converter reaches a compensated peak-current threshold, wherein the compensated peak-current threshold compensates for charging-phase loop delay. A discharging phase is terminated when the inductor current reaches a compensated valley-current threshold, wherein the compensated valley-current threshold compensates for discharging-phase loop delay.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: Jitendra Prabhakar Harshey, Hendrik Johannes Bergveld, Edevaldo Pereira da Silva Junior, Koteswararao Nannapaneni, Uday Kumar Sajja
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Patent number: 11038427Abstract: A DC-DC converter operates in a burst mode having at least one charge cycle with a charging phase followed by a discharging phase. A charging phase is terminated when an inductor current flowing through an inductance connected to the DC-DC converter reaches a compensated peak-current threshold, wherein the compensated peak-current threshold compensates for charging-phase loop delay. A discharging phase is terminated when the inductor current reaches a compensated valley-current threshold, wherein the compensated valley-current threshold compensates for discharging-phase loop delay.Type: GrantFiled: January 6, 2020Date of Patent: June 15, 2021Assignee: NXP B.V.Inventors: Jitendra Prabhakar Harshey, Hendrik Johannes Bergveld, Edevaldo Pereira da Silva, Jr., Koteswararao Nannapaneni, Uday Kumar Sajja
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Patent number: 10784783Abstract: A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold.Type: GrantFiled: January 8, 2020Date of Patent: September 22, 2020Assignee: NXP B.V.Inventors: Jitendra Prabhakar Harshey, Hendrik Johannes Bergveld, Olivier Trescases, Edevaldo Pereira da Silva Junior, Stefano Pietri, Oscar Igor Robles Palacios
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Patent number: 10720838Abstract: Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.Type: GrantFiled: June 5, 2019Date of Patent: July 21, 2020Assignee: NXP B.V.Inventors: Jitendra Prabhakar Harshey, Olivier Trescases, Edevaldo Pereira Da Silva Junior, Stefano Pietri, Jurgen Geerlings, Hendrik Johannes Bergveld
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Patent number: 9837897Abstract: A buck converter is described having a buck converter output for outputting an output supply voltage; a first power supply domain operably coupled to a power source; a second power supply domain; a power supply controller coupled to the first power supply domain, the second power supply domain and the buck converter output; wherein the power supply controller is configured to supply power to the second power supply domain from the first power supply domain or the buck converter output, in dependence of the buck converter output supply voltage. Changing the current supplied to the second power supply domain to the buck converter output may reduce the quiescent current consumption from a battery power source, prolonging battery life.Type: GrantFiled: June 13, 2016Date of Patent: December 5, 2017Assignee: NXP B.V.Inventors: Jitendra Prabhakar Harshey, Ramesh Karpur, Pankaj Agrawal
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Publication number: 20160380534Abstract: A buck converter is described having a buck converter output for outputting an output supply voltage; a first power supply domain operably coupled to a power source; a second power supply domain; a power supply controller coupled to the first power supply domain, the second power supply domain and the buck converter output; wherein the power supply controller is configured to supply power to the second power supply domain from the first power supply domain or the buck converter output, in dependence of the buck converter output supply voltage. Changing the current supplied to the second power supply domain to the buck converter output may reduce the quiescent current consumption from a battery power source, prolonging battery life.Type: ApplicationFiled: June 13, 2016Publication date: December 29, 2016Inventors: Jitendra Prabhakar Harshey, Ramesh Karpur, Pankaj Agrawal