Patents by Inventor Jitesh Vaswani

Jitesh Vaswani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230216452
    Abstract: An RF amplifier includes an amplifier input, a transistor die with a transistor and a transistor input terminal, a fundamental frequency impedance matching circuit coupled between the amplifier input and the transistor input terminal, and a harmonic frequency termination circuit coupled between the transistor input terminal and a ground reference node. The harmonic frequency termination circuit includes a first inductance coupled between the transistor input terminal and a first node, and a tank circuit coupled between the first node and the ground reference node. The tank circuit includes a first capacitance coupled between the first node and the ground reference node, and a second inductance coupled between the first node and the ground reference node. The tank circuit is configured to shunt signal energy at or near a second harmonic frequency, while appearing as an open circuit to signal energy at a fundamental frequency of operation of the RF amplifier.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Inventors: Jitesh Vaswani, Sai Sunil Mangaonkar, Aniket Anant Wadodkar
  • Patent number: 11049837
    Abstract: A packaged radio frequency (RF) amplifier device includes a flange and a transistor die mounted to the flange. The transistor die includes an output terminal. The packaged RF amplifier device includes a first bond wire array including a first plurality of bond wires. Each bond wire in the first plurality of bond wires is electrically coupled to the output terminal of the transistor die. A first ground loop area of a first bond wire in the first plurality of bond wires is greater than a second ground loop area of a second bond wire in the first plurality of bond wires.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: NXP USA, Inc.
    Inventors: Jitesh Vaswani, Scott Duncan Marshall, Ricardo Uscola
  • Publication number: 20210035942
    Abstract: A packaged radio frequency (RF) amplifier device includes a flange and a transistor die mounted to the flange. The transistor die includes an output terminal. The packaged RF amplifier device includes a first bond wire array including a first plurality of bond wires. Each bond wire in the first plurality of bond wires is electrically coupled to the output terminal of the transistor die. A first ground loop area of a first bond wire in the first plurality of bond wires is greater than a second ground loop area of a second bond wire in the first plurality of bond wires.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Jitesh VASWANI, Scott Duncan MARSHALL, Ricardo USCOLA
  • Patent number: 10707180
    Abstract: A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: July 7, 2020
    Assignee: NXP USA, INC.
    Inventors: Ricardo Uscola, Michele Lynn Miera, Sai Sunil Mangaonkar, Jitesh Vaswani
  • Publication number: 20190326233
    Abstract: A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Ricardo Uscola, Michele Lynn Miera, Sai Sunil Mangaonkar, Jitesh Vaswani