Patents by Inventor Jiun-Jie Huang
Jiun-Jie Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230361062Abstract: A semiconductor device includes a device layer, a first passivation layer, an aluminum pad, a second passivation layer, an under-ball metallurgy (UBM) pad and a connector. The device layer is disposed over a substrate, wherein the device layer includes a top metal feature. The first passivation layer is disposed over the device layer. The aluminum pad penetrates through the first passivation layer and is electrically connected to the top metal feature. The second passivation layer is disposed over the aluminum pad. The UBM pad penetrates through the second passivation layer and is electrically connected to the aluminum pad. The connector is disposed over the UBM pad. In some embodiments, a first included angle between a sidewall and a bottom of the aluminum pad is greater than a second included angle between a sidewall and a bottom of the UBM pad.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Huan Fu, Ying-Tsung Chen, Jiun-Jie Huang, Wen-Han Hung, Jen-Pan Wang
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Publication number: 20230166141Abstract: This disclosure is directed to a flameproof electronic device having a housing, an electronic assembly, and a thermal-expandable structure. The housing has a pair of vents. The electronic assembly is accommodated in the housing, at least a part of the electronic assembly is spaced from the housing to enclose a flow channel between the electronic component and an internal surface of the housing, and the flow channel communicates with the vent. The thermal-expandable structure covers the internal surface of the housing or an external surface of the electronic assembly. The heat-expandable structure expands to block the flow channel when being heated to greater than or equal to a predetermined temperature.Type: ApplicationFiled: October 27, 2022Publication date: June 1, 2023Inventors: Jiun-Jie HUANG, Chin LIEN, Yu-Chi JEN, Chih-Chiang CHAN
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Patent number: 10608094Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.Type: GrantFiled: January 23, 2018Date of Patent: March 31, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Tsun Tsai, I-Chih Chen, Chih-Mu Huang, Jiun-Jie Huang, Jen-Pan Wang
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Publication number: 20190229199Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.Type: ApplicationFiled: January 23, 2018Publication date: July 25, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Tsun Tsai, I-Chih Chen, Chih-Mu Huang, Jiun-Jie Huang, Jen-Pan Wang
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Patent number: 9837348Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.Type: GrantFiled: July 27, 2015Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang
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Publication number: 20150333003Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Jiun-Jie Huang, Ling-Sung Wang
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Patent number: 9105634Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.Type: GrantFiled: June 29, 2012Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang
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Patent number: 9064841Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.Type: GrantFiled: October 7, 2011Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Patent number: 8648341Abstract: Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.Type: GrantFiled: February 23, 2012Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yuan Yang, Jen-Pan Wang, Jiun-Jie Huang
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Publication number: 20140001597Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun-Jie Huang, Ling-Sung Wang
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Publication number: 20130306357Abstract: Disclosed is an epoxy resin composition for printed circuit board, which includes (A) an epoxy resin comprising a dicyclopentadiene type epoxy resin; (B) a copolymer of styrene and maleic anhydride as a curing agent; (C) a curing accelerator; (D) an optional silane dispersing agent; (E) an optional phosphorous-containing flame retardant; (F) an optional toughening agent; and (G) an optional inorganic filler.Type: ApplicationFiled: July 26, 2013Publication date: November 21, 2013Applicant: Taiwan Union Technology CorporationInventors: Hsuan Hao HSU, Jiun Jie HUANG, Mei Ling CHU, Hsien Te CHEN
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Patent number: 8558350Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.Type: GrantFiled: October 14, 2011Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130221353Abstract: Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yuan Yang, Jen-Pan Wang, Jiun-Jie Huang
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Patent number: 8476629Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.Type: GrantFiled: September 27, 2011Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Patent number: 8468474Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.Type: GrantFiled: September 14, 2012Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20130143046Abstract: Disclosed is an epoxy resin composition, which includes (A) an epoxy resin having at least two epoxy groups in one molecule; (B) a curing agent; and (C) polystyrene.Type: ApplicationFiled: February 27, 2012Publication date: June 6, 2013Inventors: HSIEN TE CHEN, JIUN JIE HUANG, CHIH WEI LIAO
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Publication number: 20130093047Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130087885Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130075725Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20130024833Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang