Patents by Inventor Jiun-Peng Wu
Jiun-Peng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11239340Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: June 8, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Publication number: 20200303516Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Tai-I YANG, Tien-Lu LIN, Wai-Yi LIEN, Chih-Hao WANG, Jiun-Peng WU
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Patent number: 10680078Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: January 7, 2019Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 10347746Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.Type: GrantFiled: February 3, 2017Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tetsu Ohtou, Jiun-Peng Wu, Ching-Wei Tsai
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Publication number: 20190157423Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: January 7, 2019Publication date: May 23, 2019Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 10177242Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: July 3, 2017Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Publication number: 20170301775Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: July 3, 2017Publication date: October 19, 2017Inventors: Tai-I Yang, Tien-Lu LIN, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 9711595Abstract: A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes.Type: GrantFiled: April 19, 2016Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun-Peng Wu, Tetsu Ohtou, Ching-Wei Tsai, Chih-Hao Wang, Chi-Wen Liu
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Patent number: 9698242Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: June 10, 2016Date of Patent: July 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Publication number: 20170148899Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region; a drain region aligned substantially vertically to the source region; a channel structure bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: Tetsu Ohtou, Jiun-Peng Wu, Ching-Wei Tsai
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Patent number: 9570612Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (140); a drain region (190) aligned substantially vertically to the source region; a channel structure (160) bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure (170) arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels (161) extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor (240) interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.Type: GrantFiled: June 27, 2014Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tetsu Ohtou, Jiun-Peng Wu, Ching-Wei Tsai
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Publication number: 20160293729Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: June 10, 2016Publication date: October 6, 2016Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Publication number: 20160233302Abstract: A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes.Type: ApplicationFiled: April 19, 2016Publication date: August 11, 2016Inventors: JIUN-PENG WU, TETSU OHTOU, CHING-WEI TSAI, CHIH-HAO WANG, CHI-WEN LIU
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Patent number: 9373544Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: GrantFiled: March 13, 2014Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
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Patent number: 9337263Abstract: A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed.Type: GrantFiled: June 24, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jiun-Peng Wu, Tetsu Ohtou, Ching-Wei Tsai, Chih-Hao Wang, Chi-Wen Liu
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Publication number: 20150380555Abstract: Method and structure for enhancing channel performance in a vertical gate all-around device, which provides a device comprising: a source region (140); a drain region (190) aligned substantially vertically to the source region; a channel structure (160) bridging between the source region and the drain region and defining a substantially vertical channel direction; and a gate structure (170) arranged vertically between the source region and the drain region and surrounding the channel structure. The channel structure comprises a plurality of channels (161) extending substantially vertically abreast each other, each bridging the source region and the drain region, and at least one stressor (240) interposed between each pair of adjacent channels and extending substantially along the vertical channel direction; the stressor affects lateral strain on the adjacent channels, thereby straining the channels in the vertical channel direction.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: TETSU OHTOU, JIUN-PENG WU, CHING-WEI TSAI
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Publication number: 20150372082Abstract: A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed.Type: ApplicationFiled: June 24, 2014Publication date: December 24, 2015Inventors: JIUN-PENG WU, TETSU OHTOU, CHING-WEI TSAI, CHIH-HAO WANG, CHI-WEN LIU
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Publication number: 20150262876Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu