Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.

Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.