Patents by Inventor Jiun-Wei Tsai

Jiun-Wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990351
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Patent number: 11956938
    Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
  • Publication number: 20240113119
    Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu
  • Publication number: 20040069017
    Abstract: A display element has a luminescent body formed on a glass substrate, a glass cap with the rim bonded to the rim of the glass substrate, and a sealing layer of frit formed on the bonding region between the glass substrate and the glass cap. In encapsulating, the display element is placed between a pedestal an a pressing plate, and then a high-power laser beam is provided to penetrate the glass cap to focus on the sealing layer, resulting in sintering frit. Also, pressure is applied to the pedestal and the pressing plate.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 15, 2004
    Applicant: DELTA OPTOELECTRONICS INC.
    Inventors: Chien-Hsing Li, Chun-Chien Chen, Jiun-Wei Tsai, Cheng-Nan Yeh, Lai-Cheng Chen
  • Publication number: 20030066311
    Abstract: A display element has a luminescent body formed on a glass substrate, a glass cap with the rim bonded to the rim of the glass substrate, and a sealing layer of frit formed on the bonding region between the glass substrate and the glass cap. In encapsulating, the display element is placed between a pedestal an a pressing plate, and then a high-power laser beam is provided to penetrate the glass cap to focus on the sealing layer, resulting in sintering frit. Also, pressure is applied to the pedestal and the pressing plate.
    Type: Application
    Filed: December 28, 2001
    Publication date: April 10, 2003
    Inventors: Chien-Hsing Li, Chun-Chien Chen, Jiun-Wei Tsai, Cheng-Nan Yeh, Lai-Cheng Chen