Patents by Inventor Jo Fei Wang
Jo Fei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8685759Abstract: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.Type: GrantFiled: November 3, 2010Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jo Fei Wang, Sunny Wu, Jong-I Mou
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Publication number: 20140074258Abstract: A method of automatically determining process parameters for processing equipment includes processing at least one first substrate in the processing equipment at a first time; and processing at least one second substrate in the processing equipment at a second time. The method includes collecting data on process monitors for the at least one first substrate; and the at least one second substrate. The method includes receiving the data by a multiple-input-multiple-output (MIMO) optimization system. The method includes revising a sensitivity matrix, by a MIMO optimizer, using the data and an adaptive-learning algorithm, wherein the adaptive-learning algorithm revises the sensitivity matrix based on a learning parameter which is related to a rate of change of the processing equipment over time. The method includes determining a set of process parameters for the processing equipment by the MIMO optimizer, wherein the MIMO optimizer uses the revised sensitivity matrix to determine the process parameters.Type: ApplicationFiled: November 15, 2013Publication date: March 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Feng TSAI, Chia-Tong HO, Sunny WU, Jo Fei WANG, Jong-I MOU
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Publication number: 20140067324Abstract: The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Tze-Liang Lee, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 8606387Abstract: A MIMO optimizer is used to identify tunable process parameters for processing equipment.Type: GrantFiled: January 14, 2011Date of Patent: December 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou
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Publication number: 20130306621Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tien Chang, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 8549012Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.Type: GrantFiled: May 12, 2010Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Jin-Ning Sung, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
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Publication number: 20130150997Abstract: A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Publication number: 20130144423Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING, CO., LTD.Inventors: Chih-Wei HSU, Mei-Jen WU, Yen-Di TSEN, Jo Fei WANG, Jong-I MOU, Chin-Hsiang LIN
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Publication number: 20130144419Abstract: A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
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Patent number: 8452439Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.Type: GrantFiled: March 15, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sunny Wu, Chun-Hsien Lin, Kun-Ming Chen, Dung-Yian Hsieh, Hui-Ru Lin, Jo Fei Wang, Jong-I Mou, I-Ching Chu
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Patent number: 8404572Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.Type: GrantFiled: February 13, 2009Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Patent number: 8396583Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance.Type: GrantFiled: March 25, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Andy Tsen, Jo Fei Wang, Jong-I Mou
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Publication number: 20130013097Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
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Patent number: 8295965Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.Type: GrantFiled: July 19, 2010Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
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Publication number: 20120239178Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sunny Wu, Chun-Hsien Lin, Kun-Ming Chen, Dung-Yian Hsieh, Hui-Ru Lin, Jo Fei Wang, Jong-I Mou, I-Ching Chu
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Patent number: 8239056Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.Type: GrantFiled: November 11, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Hsu, Yu-Jen Cheng, Wen-Pin Liu, Shun-Ping Wang, Shin-Rung Lu, Jo Fei Wang, Jong-I Mou, Andy Tsen, Chun-Hsien Lin
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Patent number: 8205173Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.Type: GrantFiled: June 17, 2010Date of Patent: June 19, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunny Wu, Yen-Di Tsen, Monghsung Chuang, Fu-Min Huang, Jo Fei Wang, Jong-I Mou
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Publication number: 20120130525Abstract: A MIMO optimizer is used to identify tunable process parameters for processing equipment.Type: ApplicationFiled: January 14, 2011Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Feng TSAI, Chia-Tong HO, Sunny WU, Jo Fei WANG, Jong-I MOU
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Patent number: 8108060Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.Type: GrantFiled: May 13, 2009Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andy Tsen, Jo Fei Wang, Po-Feng Tsai, Ming-Yu Fan, Jill Wang, Jong-I Mou, Sunny Wu
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Publication number: 20120016509Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.Type: ApplicationFiled: July 19, 2010Publication date: January 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou