Patents by Inventor Jo Lin

Jo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Publication number: 20240077694
    Abstract: A head-mounted device may include optical assemblies for presenting images to a user. Motors may be used to adjust the spacing between the optical assemblies to accommodate different interpupillary distances. The head-mounted device may have a housing that receives a custom-fit removable light seal with vision correction lenses. A sensor or wireless transceiver in the housing may receive interpupillary distance information from the light seal. Based on this information, the motors may adjust the optical assemblies so that the optical assemblies are spaced apart by an amount that matches the interpupillary distance associated with the user of the custom-fit removable light seal.
    Type: Application
    Filed: June 23, 2023
    Publication date: March 7, 2024
    Inventors: Elias Izpisua-Rodriguez, Wey-Jiun Lin, Forrest C Wang, Yoonhoo Jo
  • Publication number: 20240038688
    Abstract: A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11817399
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Grant
    Filed: June 6, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230307251
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 28, 2023
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 11699598
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20220245593
    Abstract: Provided herein is an engagement and care support platform (“ECSP”) computer system including at least one processor in communication with at least one memory device for facilitating senior user engagement. The processor is programmed to: (i) register a user through an application, (ii) register a caregiver associated with the user through the application, (iii) generate a senior profile based upon user personal and scheduling data, (iv) build a daily interactive user interface that reflects the senior profile, (v) display the daily interactive user interface at a first client device associated with the user, (vi) cause the first client device to initiate a daily interaction prompt to the user, (vii) determine whether any user interaction was received in response to the daily interaction prompt, and (viii) transmit a daily update message to a second client device associated with the caregiver, including an indication of whether any user interaction was received.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Michael DiBenedetto, Audrey Schwartz, Sydney Volk, Daniel Davidson, Daniel Wilson, Jo-Jo Lin, Zaki Goumandakoye
  • Publication number: 20220246292
    Abstract: Provided herein is an engagement and care support platform (“ECSP”) computer system including at least one processor in communication with at least one memory device for facilitating senior user engagement. The processor is programmed to: (i) register a user through an application, (ii) register a caregiver associated with the user through the application, (iii) generate a senior profile based upon user personal and scheduling data, (iv) build a daily interactive user interface that reflects the senior profile, (v) display the daily interactive user interface at a first client device associated with the user, (vi) cause the first client device to initiate a daily interaction prompt to the user, (vii) determine whether any user interaction was received in response to the daily interaction prompt, and (viii) transmit a daily update message to a second client device associated with the caregiver, including an indication of whether any user interaction was received.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Michael DiBenedetto, Audrey Schwartz, Sydney Volk, Daniel Davidson, Daniel Wilson, Jo-Jo Lin, Zaki Goumandakoye
  • Publication number: 20210296262
    Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.
    Type: Application
    Filed: June 6, 2021
    Publication date: September 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 11031351
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210134611
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10867811
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20190172796
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10204870
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20180350629
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20170317034
    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.
    Type: Application
    Filed: October 8, 2016
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng LIU, Jo-Lin LAN, Yu-Hsiang HU, Hung-Jui KUO
  • Publication number: 20170110421
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Application
    Filed: June 1, 2016
    Publication date: April 20, 2017
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 9471414
    Abstract: Techniques for detecting and addressing performance issues related to a mobile application are provided. Examples of performance issues include a backend service (to which the mobile application is configured to transmit requests) becoming unavailable or overloaded, a third-party service that the mobile application relies on for data pertaining to the backend service becoming unavailable, and security vulnerabilities or code irregularities in the code of the mobile application. A fallback service that is separate from the backend service detects the performance issues and sends fallback data to the mobile application. The fallback data may cause the mobile application to operate in an offline mode, where the mobile application requests locally stored data instead of transmitting data requests to the backend service. The fallback data may reference page views that the mobile application downloads and displays instead of other page views that are based on data from the backend service.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 18, 2016
    Assignee: Apollo Education Group, Inc.
    Inventors: David Le, Manish Upendran, Ted Wong, Jo-Jo Lin, Bryce Griner, Isabel George
  • Publication number: 20160048418
    Abstract: Techniques for detecting and addressing performance issues related to a mobile application are provided. Examples of performance issues include a backend service (to which the mobile application is configured to transmit requests) becoming unavailable or overloaded, a third-party service that the mobile application relies on for data pertaining to the backend service becoming unavailable, and security vulnerabilities or code irregularities in the code of the mobile application. A fallback service that is separate from the backend service detects the performance issues and sends fallback data to the mobile application. The fallback data may cause the mobile application to operate in an offline mode, where the mobile application requests locally stored data instead of transmitting data requests to the backend service. The fallback data may reference page views that the mobile application downloads and displays instead of other page views that are based on data from the backend service.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 18, 2016
    Inventors: David Le, Manish Upendran, Ted Wong, Jo-Jo Lin, Bryce Griner, Isabel George