Patents by Inventor JO UMEZAWA

JO UMEZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230075929
    Abstract: An object of the present technology is to prevent damage in a bonded portion between a semiconductor chip and a substrate in a semiconductor device in which the semiconductor chip is mounted on the substrate. A terminal is disposed between an electrode of an element and an electrode of a substrate on which the element is mounted, and electrically connects the electrode of the element and the electrode of the substrate. The terminal includes a plurality of unit lattices and a coupling portion. The unit lattices included in the terminal are formed by bonding a plurality of beams in a cube shape. The coupling portion included in the terminal couples adjacent unit lattices among the plurality of unit lattices.
    Type: Application
    Filed: January 15, 2021
    Publication date: March 9, 2023
    Inventors: JO UMEZAWA, MATTHEW LAWRENSON, BERNADETTE ELLIOTT-BOWMAN, CHRISTOPHER WRIGHT, TIMOTHY BEARD
  • Publication number: 20220262841
    Abstract: Circuits are added while an increase in size of a semiconductor package is prevented. The semiconductor package includes a transparent member; an embedding resin; an embedded circuit; and a solid-state image pickup element. In the semiconductor package, the embedding resin is formed around the transparent member. Further, in the semiconductor package, the embedded circuit is embedded in the embedding resin. Further, in the semiconductor package, the solid-state image pickup element performs photoelectric conversion on light that has passed through the transparent member and thereby generates image data.
    Type: Application
    Filed: May 22, 2020
    Publication date: August 18, 2022
    Inventors: HIROYUKI SHIGETA, KOHYOH HOSOKAWA, JO UMEZAWA, MASAKI HATANO, HIROFUMI MAKINO, TOSHIKI KOYAMA
  • Patent number: 11069654
    Abstract: A metal frame that is used in a dummy wafer in which chip-like semiconductor elements and a rewiring layer are integrated. A plurality of openings in which the chip-like semiconductor elements are disposed are formed in the metal plate, and a lattice structure is formed with the frames that are the portions between adjacent openings of the plurality of openings. Of the frames forming the lattice structure, the frames located in dicing areas of the dummy wafer are arranged in a discontinuous manner.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 20, 2021
    Assignee: SONY CORPORATION
    Inventor: Jo Umezawa
  • Publication number: 20200321312
    Abstract: A metal frame that is used in a dummy wafer in which chip-like semiconductor elements and a rewiring layer are integrated. A plurality of openings in which the chip-like semiconductor elements are disposed are formed in the metal plate, and a lattice structure is formed with the frames that are the portions between adjacent openings of the plurality of openings. Of the frames forming the lattice structure, the frames located in dicing areas of the dummy wafer are arranged in a discontinuous manner.
    Type: Application
    Filed: May 10, 2017
    Publication date: October 8, 2020
    Inventor: JO UMEZAWA
  • Publication number: 20200006207
    Abstract: A semiconductor device includes a wiring board and a chip-shaped semiconductor element flip-chip mounted on the wiring board, in which a plurality of solder bumps and a plurality of protrusions including an insulating material are provided on a surface of the chip-shaped semiconductor element on a side facing the wiring board, and the chip-shaped semiconductor element is arranged so as to face the wiring board via an underfilling material in a state in which the underfilling material having a characteristic that viscosity decreases with an increase in temperature is applied to the wiring board and then subjected to reflow treatment to be flip-chip mounted on the wiring board.
    Type: Application
    Filed: January 19, 2018
    Publication date: January 2, 2020
    Inventors: JO UMEZAWA, HIROKI TSUNEMI