Patents by Inventor Joachim Nuetzel
Joachim Nuetzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7763513Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.Type: GrantFiled: September 9, 2005Date of Patent: July 27, 2010Assignee: Qimonda AGInventors: Peng-Fei Wang, Joachim Nuetzel, Rolf Weis, Till Schloesser, Marc Strasser, Hannes Luyken
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Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
Patent number: 7442609Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.Type: GrantFiled: September 9, 2005Date of Patent: October 28, 2008Assignee: Infineon Technologies AGInventors: Peng-Fei Wang, Joachim Nuetzel, Rolf Weis, Till Schloesser, Marc Strasser, Richard Johannes Luyken -
Patent number: 7341875Abstract: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrodes devices (43, 44).Type: GrantFiled: May 21, 2002Date of Patent: March 11, 2008Assignee: Infineon Technologies AGInventors: Joachim Nuetzel, Till Schloesser, Siegfried Schwarzl, Stefan Wurn
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Publication number: 20070194301Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.Type: ApplicationFiled: November 24, 2004Publication date: August 23, 2007Inventors: Recai Sezi, Andreas Walter, Reimund Engl, Anna Maltenberger, Christine Dehm, Sitaram Arkalgud, Igor Kasko, Joachim Nuetzel, Jakob Kriz, Thomas Mikolajick, Cay-Uwe Pinnow
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Publication number: 20070176253Abstract: A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.Type: ApplicationFiled: January 31, 2006Publication date: August 2, 2007Inventors: Peng-Fei Wang, Rolf Weis, Joachim Nuetzel, Arnd Scholz, Alexander Sieck, Sigurd Zehner
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Publication number: 20070082413Abstract: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrode devices (43, 44).Type: ApplicationFiled: May 21, 2002Publication date: April 12, 2007Inventors: Joachim Nuetzel, Till Schloesser, Siegfried Schwarzl, Stefan Wurn
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Publication number: 20070057301Abstract: A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.Type: ApplicationFiled: September 9, 2005Publication date: March 15, 2007Inventors: Peng-Fei Wang, Joachim Nuetzel, Rolf Weis, Till Schloesser, Marc Strasser, Hannes Luyken
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Patent number: 7183130Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.Type: GrantFiled: July 29, 2003Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Joachim Nuetzel, Xian Jay Ning, William C. Wille
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Publication number: 20060110884Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between the two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.Type: ApplicationFiled: September 9, 2005Publication date: May 25, 2006Inventors: Peng-Fei Wang, Joachim Nuetzel, Rolf Weis, Till Schloesser, Marc Strasser, Hannes Luyken
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Patent number: 6913990Abstract: A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices to gain silicon floor space and allow maximum use of wiring levels. The method deposits a sacrificial or dummy layer of dielectric material such as SiO2 to form dummy fill structures prior to the planarization steps. The insulative dummy fill structures allow the use of less precise lithography and etching methods. The dummy fill structures provide support during the CMP process that planarizes the active devices prior to depositing another layer of SiO2 and etching lines of metallization. Since the dummy structures are made of a dielectric rather than conductive materials, the risk of shorts between levels of metallization and between active devices and lines of metallization is reduced.Type: GrantFiled: July 28, 2003Date of Patent: July 5, 2005Assignee: Infineon Technologies AGInventor: Joachim Nuetzel
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Publication number: 20050088895Abstract: Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.Type: ApplicationFiled: July 23, 2004Publication date: April 28, 2005Inventors: Dirk Manger, Till Schloesser, Rolf Weis, Bernd Goebel, Wolfgang Mueller, Joachim Nuetzel, Klaus Muemmler
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Publication number: 20050051820Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.Type: ApplicationFiled: September 10, 2003Publication date: March 10, 2005Inventors: George Stojakovic, Rajiv Ranade, Ihar Kasko, Joachim Nuetzel, Keith Milkove, Russell Allen, Young Lee, Kim Lee
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Patent number: 6858441Abstract: A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).Type: GrantFiled: September 4, 2002Date of Patent: February 22, 2005Assignee: Infineon Technologies AGInventors: Joachim Nuetzel, Xian J. Ning, Kia-Seng Low, Gill Yong Lee, Rajiv M. Ranade, Ravikumar Ramachandran
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Publication number: 20050026341Abstract: A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices to gain silicon floor space and allow maximum use of wiring levels. The method deposits a sacrificial or dummy layer of dielectric material such as SiO2 to form dummy fill structures prior to the planarization steps. The insulative dummy fill structures allow the use of less precise lithography and etching methods. The dummy fill structures provide support during the CMP process that planarizes the active devices prior to depositing another layer of SiO2 and etching lines of metallization. Since the dummy structures are made of a dielectric rather than conductive materials, the risk of shorts between levels of metallization and between active devices and lines of metallization is reduced.Type: ApplicationFiled: July 28, 2003Publication date: February 3, 2005Inventor: Joachim Nuetzel
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Publication number: 20050023581Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.Type: ApplicationFiled: July 29, 2003Publication date: February 3, 2005Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Joachim Nuetzel, Xian Jay Ning, William Wille
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Patent number: 6812141Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.Type: GrantFiled: July 1, 2003Date of Patent: November 2, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Michael C. Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O'Sullivan, Gregory Costrini, Stephen L. Brown, Frank Findeis, Chanro Park
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Patent number: 6784091Abstract: A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.Type: GrantFiled: June 5, 2003Date of Patent: August 31, 2004Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Joachim Nuetzel, Christian Arndt, Greg Costrini, Michael C. Gaidis, Xian Jay Ning
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Publication number: 20040043579Abstract: A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).Type: ApplicationFiled: September 4, 2002Publication date: March 4, 2004Inventors: Joachim Nuetzel, Xian J. Ning, Kia-Seng Low, Gill Yong Lee, Rajiv M. Ranade, Ravikumar Ramachandran
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Patent number: 6440753Abstract: A method of patterning conductive lines (252) of a memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).Type: GrantFiled: April 2, 2001Date of Patent: August 27, 2002Assignee: Infineon Technologies North America Corp.Inventors: Xian J. Ning, Joachim Nuetzel
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Publication number: 20020098676Abstract: memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).Type: ApplicationFiled: April 2, 2001Publication date: July 25, 2002Inventors: Xian J. Ning, Joachim Nuetzel