Patents by Inventor Joachim Pistorius
Joachim Pistorius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9292474Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.Type: GrantFiled: August 1, 2013Date of Patent: March 22, 2016Assignee: Altera CorporationInventors: Erhard Joachim Pistorius, Michael D. Hutton
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Patent number: 8863065Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.Type: GrantFiled: May 6, 2010Date of Patent: October 14, 2014Assignee: Altera CorporationInventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius
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Patent number: 8719753Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.Type: GrantFiled: February 10, 2010Date of Patent: May 6, 2014Assignee: Altera CorporationInventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius
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Patent number: 8521801Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.Type: GrantFiled: April 28, 2008Date of Patent: August 27, 2013Assignee: Altera CorporationInventors: Erhard Joachim Pistorius, Michael D. Hutton
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Patent number: 8161469Abstract: Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.Type: GrantFiled: December 13, 2005Date of Patent: April 17, 2012Assignee: Altera CorporationInventors: Mihail Iotov, Erhard Joachim Pistorius, Jim Park, David Karchmer
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Patent number: 7804325Abstract: To improve interfacing between a block of dedicated function circuitry and blocks of more general purpose circuitry on an integrated circuit (“IC”), signals that are to be output by the dedicated function block are routed internally in that block so that they go into interconnection circuitry on the IC for more efficient application by that interconnection circuitry to the general purpose circuitry. Some of this routing internal to the dedicated function block may be controllably variable. The routing internal to the dedicated function block may also be arranged to take advantage of “sneak” connections that may exist between the dedicated function block and the general purpose blocks.Type: GrantFiled: April 22, 2008Date of Patent: September 28, 2010Assignee: Altera CorporationInventors: Erhard Joachim Pistorius, Michael D. Hutton
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Patent number: 7701252Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.Type: GrantFiled: March 3, 2008Date of Patent: April 20, 2010Assignee: Altera CorporationInventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius
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Publication number: 20090271465Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Erhard Joachim Pistorius, Michael D. Hutton
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Patent number: 7337100Abstract: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass.Type: GrantFiled: June 12, 2003Date of Patent: February 26, 2008Assignee: Altera CorporationInventors: Michael D. Hutton, Joachim Pistorius, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Yean-Yow Hwang