Patents by Inventor Joachim Weyers
Joachim Weyers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876133Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.Type: GrantFiled: September 29, 2021Date of Patent: January 16, 2024Assignee: Infineon Technologies AGInventors: Joachim Weyers, Franz Hirler, Wolfgang Jantscher, David Kammerlander, Ralf Siemieniec
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Publication number: 20230326974Abstract: A semiconductor diode includes a wide bandgap semiconductor body having opposing first and second surfaces. The wide band gap semiconductor body includes a first pn junction diode having a first p-doped region adjoining the first surface and a first n-doped region adjoining both surfaces. The semiconductor diode further includes a semiconductor element including a second pn junction diode having a second p-doped region and second n-doped region, and a dielectric structure between the wide bandgap semiconductor body and semiconductor element. The dielectric structure electrically insulates the wide bandgap semiconductor body from the semiconductor element. The bandgap energy of the semiconductor element is smaller than that of the wide bandgap semiconductor body. A cathode contact is electrically connected to the first n-doped region at the second surface. The second n-doped region of the second pn junction diode is electrically coupled to the first n-doped region of the first pn junction diode.Type: ApplicationFiled: March 24, 2023Publication date: October 12, 2023Inventors: Thomas Ralf Siemieniec, Joachim Weyers, Armin Tilke
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Patent number: 11688732Abstract: A single chip power semiconductor device includes: first and second load terminals; a semiconductor body integrated in the single chip and coupled to the load terminals and configured to conduct a load current along a load current path between the load terminals; a control terminal and at least one control electrode electrically connected thereto, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; a protection structure integrated, separately from the load current path, in the single chip and including a series connection of pn junctions with first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The series connection of the pn-junctions is connected in forward bias between the control terminal and the first load terminal.Type: GrantFiled: December 14, 2020Date of Patent: June 27, 2023Assignee: Infineon Technologies Austria AGInventors: Guang Zeng, Anton Mauder, Joachim Weyers
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Publication number: 20230127508Abstract: A semiconductor device includes a transistor array and a sense pad. The transistor array includes a plurality of transistor cells electrically connected in parallel between a source electrode and a drain structure. The drain structure is formed in a semiconductor portion based on a single-crystalline wide bandgap material. A sense element formed from the wide bandgap material includes at least one rectifying junction electrically connected between the sense pad and the source electrode.Type: ApplicationFiled: October 20, 2022Publication date: April 27, 2023Inventors: Joachim Weyers, Franz Hirler
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Publication number: 20220406928Abstract: A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.Type: ApplicationFiled: June 13, 2022Publication date: December 22, 2022Inventors: Joachim Weyers, Anton Mauder, Ralf Siemieniec, Guang Zeng
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Patent number: 11430781Abstract: In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.Type: GrantFiled: January 23, 2020Date of Patent: August 30, 2022Assignee: Infineon Technologies Dresden GmbH & Co. KGInventor: Joachim Weyers
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Patent number: 11424358Abstract: A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region.Type: GrantFiled: April 2, 2020Date of Patent: August 23, 2022Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Joachim Weyers, Andreas Boehm, Franz Hirler, Enrique Vecino Vazquez
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Patent number: 11302781Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A transistor structure is formed is the semiconductor body. A trench structure extends from the first surface into the semiconductor body. An electrostatic discharge protection structure is accommodated in the trench structure. The electrostatic discharge protection structure includes a first terminal region and a second terminal region. A source contact structure at the first surface is electrically connected to source regions of the transistor structure and to the first terminal region. A gate contact structure at the first surface is electrically connected to a gate electrode of the transistor structure and to the second terminal region.Type: GrantFiled: April 12, 2018Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Joachim Weyers, Stefan Gamerith, Franz Hirler, Anton Mauder
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Publication number: 20220102549Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.Type: ApplicationFiled: September 29, 2021Publication date: March 31, 2022Inventors: Joachim Weyers, Franz Hirler, Wolfgang Jantscher, David Kammerlander, Ralf Siemieniec
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Publication number: 20220102487Abstract: A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density N2 of the buried region is higher than a mean net dopant density N1 of the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.Type: ApplicationFiled: September 29, 2021Publication date: March 31, 2022Inventors: Ralf Siemieniec, Wolfgang Jantscher, David Kammerlander, Dethard Peters, Joachim Weyers
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Publication number: 20210193646Abstract: A single chip power semiconductor device includes: first and second load terminals; a semiconductor body integrated in the single chip and coupled to the load terminals and configured to conduct a load current along a load current path between the load terminals; a control terminal and at least one control electrode electrically connected thereto, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; a protection structure integrated, separately from the load current path, in the single chip and including a series connection of pn junctions with first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The series connection of the pn-junctions is connected in forward bias between the control terminal and the first load terminal.Type: ApplicationFiled: December 14, 2020Publication date: June 24, 2021Inventors: Guang Zeng, Anton Mauder, Joachim Weyers
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Patent number: 10971620Abstract: A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.Type: GrantFiled: June 20, 2019Date of Patent: April 6, 2021Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Joachim Weyers, Andreas Boehm, Anton Mauder, Patrick Schindler, Stefan Tegen, Armin Tilke, Uwe Wahl
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Publication number: 20200321463Abstract: A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region.Type: ApplicationFiled: April 2, 2020Publication date: October 8, 2020Inventors: Joachim Weyers, Andreas Boehm, Franz Hirler, Enrique Vecino Vazquez
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Patent number: 10741541Abstract: A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.Type: GrantFiled: October 4, 2016Date of Patent: August 11, 2020Assignee: Infineon Technologies Dresden GmbHInventors: Joachim Weyers, Markus Schmitt, Armin Tilke, Stefan Tegen, Thomas Bertrams
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Publication number: 20200243505Abstract: In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.Type: ApplicationFiled: January 23, 2020Publication date: July 30, 2020Inventor: Joachim Weyers
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Publication number: 20200044064Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
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Publication number: 20200027949Abstract: A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Armin Willmeroth, Franz Hirler, Bjoern Fischer, Joachim Weyers
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Patent number: 10541327Abstract: A semiconductor device includes a trench structure extending into a semiconductor body from a first surface. The trench structure has a shield electrode, a dielectric structure and a diode structure. The diode structure is arranged at least partly between the first surface and a first part of the dielectric structure. The shield electrode is arranged between the first part of the dielectric structure and a bottom of the trench structure. The shield electrode and the semiconductor body are electrically isolated by the dielectric structure. Corresponding methods of manufacture are also described.Type: GrantFiled: April 12, 2018Date of Patent: January 21, 2020Assignee: Infineon Technologies Austria AGInventors: Joachim Weyers, Franz Hirler
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Publication number: 20190393334Abstract: A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.Type: ApplicationFiled: June 20, 2019Publication date: December 26, 2019Inventors: Joachim Weyers, Andreas Boehm, Anton Mauder, Patrick Schindler, Stefan Tegen, Armin Tilke, Uwe Wahl
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Patent number: 10504891Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides, an active area, and an inactive area which is, in a projection onto to the first and/or second side, arranged between the active area and an edge of the semiconductor body. A transistor structure in the active area includes a source region adjacent the first side and forms a first pn-junction in the semiconductor body. A gate electrode insulated from the semiconductor body is arranged adjacent to the first pn-junction. A capacitor in the inactive area includes first and second conductors arranged over each other on the first side. A source contact structure arranged above the capacitor is in Ohmic connection with the source region and the first conductor. A gate contact structure is arranged above the capacitor, spaced apart from the source contact structure and in Ohmic connection with the gate electrode and the second conductor.Type: GrantFiled: August 8, 2018Date of Patent: December 10, 2019Assignee: Infineon Technologies Austria AGInventors: Joachim Weyers, Franz Hirler, Maximilian Treiber