Patents by Inventor Joann Lam

Joann Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9734071
    Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Oracle International Corporation
    Inventors: Serena Leung, Ramaswamy Sivaramakrishnan, Joann Lam, David Smentek
  • Patent number: 9720834
    Abstract: Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating “valid” and/or “private” information), and the other reverse sub-directories for relatively low-frequency accesses updating “index” and “way” information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 1, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jinho Kwack, Joann Lam, Hoyeol Cho, Claire Ni
  • Publication number: 20170168941
    Abstract: Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating “valid” and/or “private” information), and the other reverse sub-directories for relatively low-frequency accesses updating “index” and “way” information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Jinho Kwack, Joann Lam, Hoyeol Cho, Claire Ni
  • Publication number: 20160335184
    Abstract: A method and apparatus for snooping caches is disclosed. In one embodiment, a system includes a number of processing nodes and a cache shared by each of the processing nodes. The cache is partitioned such that each of the processing nodes utilizes only one assigned partition. If a query by a processing node to its assigned partition of the cache results in a miss, a cache controller may determine whether to snoop other partitions in search of the requested information. The determination may be made based on history of where requested information was obtained from responsive to previous misses in that partition.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Serena Leung, Ramaswamy Sivaramakrishnan, Joann Lam, David Smentek
  • Patent number: 5696929
    Abstract: A flash EEPROM memory array including a cache buffer for storing lines of data being written to all addresses in main memory; a plurality of holding buffers for storing lines of data from the cache buffer addressed to a particular block of addresses in main memory; a plurality of blocks of flash EEPROM main memory for storing lines of data from a holding buffer directed to a particular block of addresses in main memory; and control circuitry for writing lines of data addressed to a particular block of addresses in main memory from the cache buffer to a holding buffer when the cache buffer fills or a holding buffer limit is reached whichever occurs first, writing valid data from an addressed block of flash memory to lines of the holding buffer not holding valid data written from the cache buffer, erasing the addressed block of flash memory, and writing all of the lines in the holding buffer to the addressed block of flash memory.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: December 9, 1997
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Asad Faizi, Joann Lam, Peter J. Ruscito