Patents by Inventor Jocelyn Francois Orion Jaubert
Jocelyn Francois Orion Jaubert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11531547Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry; register mapping circuitry to map zero or more architectural processor registers relating to execution of that program instruction to respective ones of a set of physical processor registers; commit circuitry to commit, in a program code order, the results of executed program instructions, the commit circuitry being configured to access a data store which stores register tag data to indicate which physical registers mapped by the register mapping circuitry relate to a given program instruction; fault detection circuitry to detect a memory access fault in respect of a vector memory access operation and to generate fault indication data indicative of an element earliest in the element order for which a memory access fault was detected; a fault indication register to store the fault indication data, in which the register mapping circuitry is configured to generate a register mapping for a program instruction for any architectural pType: GrantFiled: May 21, 2021Date of Patent: December 20, 2022Assignee: Arm LimitedInventors: Damian Maiorano, Luca Nassi, Cédric Denis Robert Airaud, Christophe Laurent Carbonne, Jocelyn François Orion Jaubert, Pasquale Ranone
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Publication number: 20220374240Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry; register mapping circuitry to map zero or more architectural processor registers relating to execution of that program instruction to respective ones of a set of physical processor registers; commit circuitry to commit, in a program code order, the results of executed program instructions, the commit circuitry being configured to access a data store which stores register tag data to indicate which physical registers mapped by the register mapping circuitry relate to a given program instruction; fault detection circuitry to detect a memory access fault in respect of a vector memory access operation and to generate fault indication data indicative of an element earliest in the element order for which a memory access fault was detected; a fault indication register to store the fault indication data, in which the register mapping circuitry is configured to generate a register mapping for a program instruction for any architectural pType: ApplicationFiled: May 21, 2021Publication date: November 24, 2022Inventors: Damian MAIORANO, Luca NASSI, Cédric Denis Robert AIRAUD, Christophe Laurent CARBONNE, Jocelyn François Orion JAUBERT, Pasquale RANONE
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Patent number: 10902113Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: GrantFiled: October 25, 2017Date of Patent: January 26, 2021Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Carlo Dario Fanara, Jocelyn François Orion Jaubert
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Patent number: 10572262Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: GrantFiled: July 17, 2017Date of Patent: February 25, 2020Assignee: ARM LimitedInventors: Jocelyn Francois Orion Jaubert, Frederic Jean Denis Arsanto, Guillaume Schon, Carlo Dario Fanara
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Patent number: 10540299Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: GrantFiled: June 30, 2017Date of Patent: January 21, 2020Assignee: ARM LimitedInventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Guillaume Schon, Jocelyn Francois Orion Jaubert
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Patent number: 10445500Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: GrantFiled: June 28, 2017Date of Patent: October 15, 2019Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Jocelyn François Orion Jaubert, Carlo Dario Fanara
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Publication number: 20190121967Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Carlo Dario FANARA, Jocelyn François Orion JAUBERT
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Publication number: 20190018686Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Jocelyn Francois Orion JAUBERT, Frederic Jean Denis ARSANTO, Guillaume SCHON, Carlo Dario FANARA
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Publication number: 20190004977Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Carlo Dario FANARA, Frederic Jean Denis ARSANTO, Guillaume SCHON, Jocelyn Francois Orion JAUBERT
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Publication number: 20190005240Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Jocelyn François Orion JAUBERT, Carlo Dario FANARA
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Patent number: 9513925Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: GrantFiled: September 19, 2013Date of Patent: December 6, 2016Assignee: ARM LimitedInventors: Nicolas Chaussade, Florent Begon, Melanie Emanuelle Lucie Teyssier, Remi Teyssier, Jocelyn Francois Orion Jaubert
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Patent number: 9361112Abstract: A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed.Type: GrantFiled: April 18, 2013Date of Patent: June 7, 2016Assignee: ARM LimitedInventors: Clément Marc Demongeot, Louis-Marie Vincent Mouton, Frédéric Claude Marie Piry, Jocelyn Francois Orion Jaubert, Albin Pierick Tonnerre
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Patent number: 9323536Abstract: A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack.Type: GrantFiled: May 2, 2013Date of Patent: April 26, 2016Assignee: ARM LimitedInventors: Clement Marc Demongeot, Louis-Marie Vincent Mouton, Jocelyn Francois Orion Jaubert
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Patent number: 9189432Abstract: A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.Type: GrantFiled: November 15, 2010Date of Patent: November 17, 2015Assignee: ARM LimitedInventors: Melanie Emanuelle Lucie Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Nicolas Jean Phillippe Huot
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Publication number: 20140019734Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: ApplicationFiled: September 19, 2013Publication date: January 16, 2014Applicant: ARM LIMITEDInventors: Nicolas CHAUSSADE, Florent BEGON, Melanie Emanuelle Lucie TEYSSIER, Remi TEYSSIER, Jocelyn Francois Orion JAUBERT
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Patent number: 8578139Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: GrantFiled: August 5, 2010Date of Patent: November 5, 2013Assignee: ARM LimitedInventors: Nicolas Chaussade, Florent Begon, Mélanie Emanuelle Lucie Teyssier, Rémi Teyssier, Jocelyn Francois Orion Jaubert
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Patent number: 8458532Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.Type: GrantFiled: October 27, 2010Date of Patent: June 4, 2013Assignee: ARM LimitedInventors: Jocelyn Francois Orion Jaubert, Florent Begon, Melanie Emanuelle Lucie Teyssier
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Patent number: 8352794Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.Type: GrantFiled: November 19, 2009Date of Patent: January 8, 2013Assignee: ARM LimitedInventors: Remi Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Cédric Denis Robert Airaud
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Publication number: 20120124300Abstract: A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: ARM LIMITEDInventors: Melanie Emanuelle Lucie Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Nicolas Jean Phillippe Huot
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Publication number: 20120110396Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: ARM LIMITEDInventors: Jocelyn Francois Orion Jaubert, Florent Begon, Melanie Emanuelle Lucie Teyssier