Patents by Inventor Jochen Wynants

Jochen Wynants has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230215862
    Abstract: A semiconductor device is provided including a die having an electronic component integrated thereon. The component includes regions in the die, including a first region of a first charge type electrically connected to a first device terminal, a second region of a second charge type forming a first PN junction with the first region, a third region of the first charge type forming a second PN junction with the second region, the third region being spaced apart from the first region by the second region and being electrically connected to the second device terminal, a fourth region of the first charge type forming a third PN junction with the second region, the fourth region being spaced apart from the first region and third region by the second region. The device further includes an electronic unit electrically connected between the first device terminal, the second device terminal and the fourth region.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Hans-Martin Ritter, Steffen Holland, Jochen Wynants
  • Patent number: 10957685
    Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 23, 2021
    Assignee: Nexperia B.V.
    Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas Igel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig
  • Patent number: 10643941
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 5, 2020
    Assignee: Nexperia B.V.
    Inventors: Zhihao Pan, Friedrich Hahn, Steffen Holland, Olaf Pfennigstorf, Jochen Wynants, Hans-Martin Ritter
  • Patent number: 10546816
    Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 28, 2020
    Assignee: Nexperia B.V.
    Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
  • Publication number: 20190123037
    Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Applicant: NEXPERIA B.V.
    Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas lgel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig
  • Publication number: 20180166388
    Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 14, 2018
    Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
  • Publication number: 20170170122
    Abstract: A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a dielectric partition for electrically isolating a first part of the substrate from a second part of the substrate. The dielectric partition extends through the substrate from the major surface to the backside.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 15, 2017
    Inventors: Hans-Martin Ritter, Joachim Utzig, Frank Burmeister, Godfried Henricus Josephus Notermans, Jochen Wynants, Rainer Mintzlaff
  • Publication number: 20160218058
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate provided in a chip-scale package (CSP). The device also includes a plurality of contacts provided on a major surface of the substrate. The device further includes an electrically floating metal layer forming an ohmic contact on a backside of the semiconductor substrate. The device is operable to conduct a current that passes through the substrate from a first of said plurality of contacts to a second of said plurality of contacts via the metal layer on the backside.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 28, 2016
    Inventors: Zhihao Pan, Friedrich Hahn, Steffen Holland, Olaf Pfennigstorf, Jochen Wynants, Hans-Martin Ritter
  • Patent number: 7528459
    Abstract: A monolithically integrated punch-through diode with a Schottky-like behavior. This is achieved as a Schottky-metal area (16) is deposited onto at least part of the first p-doped well's (9) surface. The Schottky-metal area (16) and the p-doped well (9) form the metal-semiconductor-transition of a Schottky-diode. The overvoltage protection of the inventive PT-diode is improved as the forward characteristic has a voltage drop that is less than 0.5V.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: May 5, 2009
    Assignee: NXP B.V.
    Inventors: Hans-Martin Ritter, Martin Lübbe, Jochen Wynants
  • Publication number: 20060158801
    Abstract: A monolithically integrated punch-through diode with a Schottky-like behavior. This is achieved as a Schottky-metal area (16) is deposited onto at least part of the first p-doped well's (9) surface. The Schottky-metal area (16) and the p-doped well (9) form the metal-semiconductor-transition of a Schottky-diode. The overvoltage protection of the inventive PT-diode is improved as the forward characteristic has a voltage drop that is less than 0.5V.
    Type: Application
    Filed: May 24, 2004
    Publication date: July 20, 2006
    Inventors: Hans-Martin Ritter, Martin Lubbe, Jochen Wynants