Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: A circuit can include a transistor coupled to a resistor or a diode. In an embodiment, the circuit can include a pair of transistors arranged in a cascode configuration, and each of the transistors can have a corresponding component connected in parallel. In a particular embodiment, the components can be resistors, and in another particular, embodiment, the components can be diodes. The circuit can have less on-state resistance as compared to a circuit in which only one of the components is used, and reduces the off-state voltage on the gate of a high-side transistor. An integrated circuit can include a high electron mobility transistor structure and a resistor, a diode, a pair of resistors, or a pair of diodes.

Abstract: A circuit can include a transistor coupled to a resistor or a diode. In an embodiment, the circuit can include a pair of transistors arranged in a cascode configuration, and each of the transistors can have a corresponding component connected in parallel. In a particular embodiment, the components can be resistors, and in another particular, embodiment, the components can be diodes. The circuit can have less on-state resistance as compared to a circuit in which only one of the components is used, and reduces the off-state voltage on the gate of a high-side transistor. An integrated circuit can include a high electron mobility transistor structure and a resistor, a diode, a pair of resistors, or a pair of diodes.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: A transistor (100) is formed on a semiconductor substrate (17) that forms a channel (27) of the transistor. A drain region (25) has a second conductivity type formed in the substrate to electrically couple to the channel. A first portion (40) of the drain region is formed with a first depth and a second portion (61) is formed between the first portion and the channel with a second depth less than the first depth. First and second field reduction regions (10, 11) have a first conductivity type and are formed in the first and second portions of the drain region. The first field reduction region is formed to a third depth and the second field reduction region is formed between the first field reduction region and the channel with a fourth depth less than the third depth.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Abstract: A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate region (105). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the “on” state. The MOSFET device further has a p-top layer (108) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with a top layer (108) of opposite conductivity. A thin layer of oxide (124) is formed over the top layer (108).

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with a top layer (108) of opposite conductivity. The doping in the top layer (108) varies laterally, increasing breakdown voltage and decreasing on-resistance.

Abstract: A high voltage MOS device (100) with multiple p-regions (110) is disclosed. The device comprises a plurality of p-regions (110) arranged as multiple segments both perpendicular to and parallel to current flow. The p-regions (110) allow for depletion in all directions when the device is blocking voltage, leading to a high breakdown voltage. During operation, the multiple regions have multiple conductivity channels (118) of high conductivity that allows current to flow, thus enhancing on-resistance.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: A high voltage device (100) is provided that has distinct field oxide regions (122) surrounded by p-top regions (108). The device is formed by first forming a p-top region (108) and then forming a patterned field oxide layer (122) over the p-top region (108). The field oxide layer (122) has open areas where the p-top region (108) is not covered by field oxide (122). The field oxide layer (122) that overlies the p-top region (108) consumes the p-top region (108) leaving exposed p-top regions (108) between the field oxide layer (122). Alternatively, the device (100) is formed by first forming a pattern of field oxide (122) on top of the device (100). Then, an implantation step is performed to form a p-top region (108). The areas of field oxide (122) block the implant. The areas where there are openings allow the formation of p-top regions (108) between the field oxide (122).

Abstract: A first conductor array (24, FIG. 5) of an electronic device (21) such as an integrated circuit is interconnected to a second conductor array (25) of a first substrate (22) by, first, using photolithographic masking and etching to make an array of substantially uniformly spaced apertures (15, FIG. 2) in a mask (11). The mask is located over a second substrate (12), and the apertures are used to form an array of substantially uniformly spaced metal particles (19). The metal particles are joined with insulative material (11) to form a layer of anisotropic conductive material (20), and the anisotropic conductive material layer is removed from the second substrate. The conductors (24) in the first conductor array of the electronic device are registered with conductors (25) of the second conductor array of the first substrate (22), and the layer of anisotropic conductive materials is compressed between the first and second conductor arrays.