Abstract: An input driver for use with a differential folder in a flash A/D converter having a static ladder that provides an array of reference voltages and a method of operation thereof. The input driver includes a differential signal driver, coupled to an AC input signal, that generates first and second complementary drive signals for a differential folder stage. A tracking circuit, coupled to the differential signal driver, is utilized to maintain a voltage at the center of the static ladder to improve common mode rejection of the input driver without reducing bandwidth. In a related embodiment, the voltage at the center of the static ladder is an average DC voltage of the first and second drive signals.

Abstract: A combined read and write VCO for data channels is disclosed. The combined read and write VCO for data channels shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase. The combined read and write VCO includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal. The adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration.

Abstract: A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for "folding" the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.

Abstract: A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for "folding" the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.

Abstract: A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for "folding" the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.

Abstract: A direct access storage device includes at least one disk mounted for rotation about an axis and having opposed disk surfaces for storing data. A magneto-resistive (MR) transducer head is mounted for movement across each respective disk surface for writing to and for reading data signals from the disk surface. Each MR transducer head includes a write element and a read element. A preamplifier, associated with the MR transducer head, amplifies read and write signals of the read element and the write element. A flex cable couples the read and write signals between the preamplifier and the MR transducer heads. The flex cable includes a common read return signal line for each sequential pair of the MR transducer heads.

Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders with a positive phase voltage source connected at the top and bottom of one of the pair of series connected resistor ladders and a negative phase voltage source connected at the top and bottom of the other one of the pair of series connected resistor ladders; both the positive phase voltage source and the negative phase voltage source including a predetermined first DC voltage value. At least one additional positive phase voltage source is connected to the one of the pair of series connected resistor ladders and at least one additional negative phase voltage source is connected to the other one of the pair of series connected resistor ladders. The additional positive phase and negative phase voltage sources include a predetermined second DC voltage value.

Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair.