Patents by Inventor Joe Olson

Joe Olson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10886279
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 5, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Publication number: 20200279852
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 10692872
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 23, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Publication number: 20200027832
    Abstract: A method of forming a device may include forming a component in a first level of a device structure; forming a contact cavity overlapping the component, the contact cavity forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane. The method may further include filling the contact cavity with a conductor, wherein an angled conductor is formed, wherein the angled conductor extends to a second level of the device structure.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson, Min Gyu Sung
  • Publication number: 20190181144
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 9934928
    Abstract: Provided herein are approaches for improving ion beam extraction stability and ion beam current for an ion extraction system. In one approach, a source housing assembly may include a source housing surrounding an ion source including an arc chamber, the source housing having an extraction aperture plate mounted at a proximal end thereof. The source housing assembly further includes a vacuum liner disposed within an interior of the source housing to form a barrier around a set of vacuum pumping apertures. As configured, openings in the source housing assembly, other than an opening in the extraction aperture plate, are enclosed by the extraction aperture plate and the vacuum liner, thus ensuring appendix arcs or extraneous ions produced outside the arc chamber remain within the source housing. Just those ions produced within the arc chamber exit the source housing through the opening of the extraction aperture plate.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 3, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Shengwu Chang, Jeff Burgess, William Leavitt, Michael St Peter, Matt Mosher, Joe Olson, Frank Sinclair
  • Publication number: 20160336138
    Abstract: Provided herein are approaches for improving ion beam extraction stability and ion beam current for an ion extraction system. In one approach, a source housing assembly may include a source housing surrounding an ion source including an arc chamber, the source housing having an extraction aperture plate mounted at a proximal end thereof. The source housing assembly further includes a vacuum liner disposed within an interior of the source housing to form a barrier around a set of vacuum pumping apertures. As configured, openings in the source housing assembly, other than an opening in the extraction aperture plate, are enclosed by the extraction aperture plate and the vacuum liner, thus ensuring appendix arcs or extraneous ions produced outside the arc chamber remain within the source housing. Just those ions produced within the arc chamber exit the source housing through the opening of the extraction aperture plate.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 17, 2016
    Inventors: Shengwu Chang, Jeff Burgess, William Leavitt, Michael St Peter, Matt Mosher, Joe Olson, Frank Sinclair
  • Patent number: 6347394
    Abstract: An integrated circuit (IC) module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Multi-Chip Module (MCM), includes a buffering IC that buffers clock and other input signals received by the IC module. As a result of the buffering, the setup and hold times associated with these input signals are improved, thereby improving yields.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: February 12, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Roland Ochoa, Joe Olson