Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a plurality of control signals and a select signal, in response to (i) a receive clock signal, (ii) a reference clock signal and (iii) a master clock signal. The second circuit may be configured to generate a read signal and a window signal in response to the plurality of control signals. The third circuit may be configured to generate a lock signal in response to (i) the reference clock signal, (ii) the select signal, (iii) the read signal and (iv) the window signal. The receive clock signal and the reference clock signal may be independent clocks configured to provide range control over one or more channels.

Abstract: A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.

Abstract: An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.