Patents by Inventor Joe W. McPherson
Joe W. McPherson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869948Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.Type: GrantFiled: February 17, 2021Date of Patent: January 9, 2024Assignee: Wolfspeed, Inc.Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
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Publication number: 20220262909Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
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Publication number: 20220140132Abstract: Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.Type: ApplicationFiled: November 4, 2020Publication date: May 5, 2022Inventors: Edward Robert Van Brunt, Joe W. McPherson, Thomas E. Harrington, III, Sei-Hyung Ryu, Brett Hull, In-Hwan Ji
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Publication number: 20110165754Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joe W. McPherson, Ajit Shanware
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Patent number: 7906405Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.Type: GrantFiled: March 13, 2008Date of Patent: March 15, 2011Assignee: Texas Instruments IncorporatedInventors: Joe W. McPherson, Ajit Shanware
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Patent number: 7888776Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.Type: GrantFiled: June 30, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
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Publication number: 20090321734Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
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Publication number: 20090161290Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.Type: ApplicationFiled: March 13, 2008Publication date: June 25, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joe W. McPherson, Ajit Shanware
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Patent number: 7402514Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: GrantFiled: January 24, 2003Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield
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Patent number: 7033924Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: GrantFiled: September 16, 2003Date of Patent: April 25, 2006Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Joe W. McPherson
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Patent number: 6967499Abstract: The present invention provides, in one aspect, a method of testing an electrical breakdown characteristic of a dielectric in a microelectronic device. This method includes determining a first dielectric breakdown voltage distribution of a first test sample by using a first voltage ramp rate, determining a second dielectric breakdown voltage distribution of a second test sample by using a second voltage ramp rate and determining a spacing distribution between conductive lines in the first and second test samples based on a field acceleration factor associated with the dielectrics of the first and second test samples, the first and second voltage ramp rates, and a difference between the first and second breakdown voltage distributions. This spacing distribution is used to determine corrected electric breakdown fields based on a measured breakdown voltage of a test sample, to improve microelectronic-device screening for interconnect dielectric reliability.Type: GrantFiled: November 12, 2004Date of Patent: November 22, 2005Assignee: Texas Instruments IncorporatedInventors: Gaddi S. Haase, Joe W. McPherson
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Patent number: 6965136Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).Type: GrantFiled: October 14, 2003Date of Patent: November 15, 2005Assignee: Texas Instruments IncorporatedInventors: Yaojian Leng, Honglin Guo, Joe W. McPherson
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Patent number: 6919219Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).Type: GrantFiled: December 13, 2002Date of Patent: July 19, 2005Assignee: Texas Instruments IncorporatedInventors: Yaojian Leng, Honglin Guo, Joe W. McPherson
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Publication number: 20040147112Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Inventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield
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Publication number: 20040099867Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).Type: ApplicationFiled: December 13, 2002Publication date: May 27, 2004Inventors: Yaojian Leng, Honglin Guo, Joe W. McPherson
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Publication number: 20040102000Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).Type: ApplicationFiled: October 14, 2003Publication date: May 27, 2004Inventors: Yaojian Leng, Honglin Guo, Joe W. McPherson
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Patent number: 6737351Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: GrantFiled: April 1, 2002Date of Patent: May 18, 2004Assignee: Texas Instruments IncorporatedInventors: Ennis T. Ogawa, Joe W. McPherson
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Publication number: 20040041274Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: ApplicationFiled: September 16, 2003Publication date: March 4, 2004Inventors: Ennis T. Ogawa, Joe W. McPherson
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Publication number: 20030122260Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.Type: ApplicationFiled: April 1, 2002Publication date: July 3, 2003Inventors: Ennis T. Ogawa, Joe W. McPherson
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Patent number: 6091114Abstract: A semiconductor device includes a first transistor (52) and gated diode (50) formed at a face of a semiconductor layer (56). The first transistor (52) includes a source region (60a), a drain region (60b), a gate oxide layer (62), and a conductive gate (64). The gated diode (54) includes a first moat region (66a), a second moat region (66b), a gate oxide layer (68), and a conductive gate (70). A first conductor (77) connects the conductive gate (70) of the gated diode (54) to the semiconductor layer (56) and a second conductor (76) connects the moat regions (66a, 66b) of the gated diode (54) to the conductive gate (64) of the first transistor (52). Gated diode (54) has a reduced breakdown voltage relative to the gate oxide layer (62) of first transistor (52) and thus establishes a leakage path to semiconductor layer (56) to direct leakage current to semiconductor layer (56), thereby inhibiting charge from accumulating on the gate oxide layer (62) of first transistor (52).Type: GrantFiled: March 31, 1998Date of Patent: July 18, 2000Assignee: Texas Instruments IncorporatedInventors: Homi C. Mogul, Joe W. McPherson, Bob Strong, Anand Seshadri