Abstract: A method for gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors is disclosed in various embodiments. According to one embodiment of the invention, a method is provided for processing a semiconductor substrate. The method includes providing a substrate containing a germanium-containing semiconductor or a compound semiconductor, and exposing the substrate to a process gas containing a sulfur-containing gas and a nitrogen-containing gas that passivates a surface of the germanium-containing semiconductor or the compound semiconductor with sulfur. According to another embodiment, the germanium-containing semiconductor or the compound semiconductor has an oxidized layer thereon and the exposing to the process gas removes the oxidized layer from the substrate. According to another embodiment, the substrate may be treated with hydrogen fluoride (HF) gas and ammonia (NH.sub.

Abstract: A method for gas phase oxide removal and passivation of germanium-containing semiconductors and compound semiconductors are disclosed in various embodiments. According to one embodiment of the invention, a method is provided for processing a semiconductor substrate. The method includes providing a substrate containing a germanium-containing semiconductor or a compound semiconductor, and exposing the substrate to a process gas containing a sulfur-containing gas and a nitrogen-containing gas that passivates a surface of the germanium-containing semiconductor or the compound semiconductor with sulfur. According to another embodiment, the germanium-containing semiconductor or the compound semiconductor has an oxidized layer thereon and the exposing to the process gas removes the oxidized layer from the substrate.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract: Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.

Abstract: Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.

Abstract: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.

Abstract: Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.

Abstract: Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.