Patents by Inventor Joel Coburn

Joel Coburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150019792
    Abstract: Systems and methods provide an efficient method for executing transactions on a storage device (e.g., a disk or solid-state disk) by using special support in the storage device for making a set of updates atomic and durable. The storage device guarantees that these updates complete as a single indivisible operation and that if they succeed, they will survive permanently despite power loss, system failure, etc. The storage device performs transaction (e.g., read/write) operations directly at storage device controllers. As a result, transactions execute with lower latency and consume less communication bandwidth between the host and the storage device. Additionally, a unique interface is provided which allows the application to manage the logs used by the hardware.
    Type: Application
    Filed: January 23, 2013
    Publication date: January 15, 2015
    Inventors: Steven Swanson, Joel Coburn, Trevor Bunker
  • Publication number: 20070101424
    Abstract: A security policy associated with a system is evaluated. The system includes a communication bus having a data bus and a plurality of components interconnected via the communication bus. The system also includes a circuit configured to evaluate a security policy associated with the system by reading at least one data bus signal associated with a transaction between at least two of the plurality of components.
    Type: Application
    Filed: July 20, 2006
    Publication date: May 3, 2007
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Srivaths Ravi, Anand Raghunathan, Srimat Chakradhar, Joel Coburn
  • Publication number: 20060058994
    Abstract: The time required to estimate the amount of power that will be consumed by a circuit under design is significantly speeded up. Specifically, the steps involved in power estimation (power model evaluation, aggregation) are implemented as power estimation circuitry that is added to the design of the functional circuit during circuit design. The resulting power-model-enhanced circuit is mapped onto a hardware emulation platform, one of whose outputs is a computation of the estimated power computed by the power estimation circuitry during the emulation. As compared to state-of-the-art commercial power estimation tools, speed-ups from around 10-fold to over 500-fold can be realized.
    Type: Application
    Filed: February 17, 2005
    Publication date: March 16, 2006
    Applicant: NEC Laboratories America, Inc.
    Inventors: Srivaths Ravi, Anand Raghunathan, Joel Coburn