Patents by Inventor Joel J. Orona

Joel J. Orona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and method of testing failed or returned die to determine failure location and type
    Patent number: 6768329
    Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed form necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: July 27, 2004
    Assignee: Xilinx Inc.
    Inventors: S. Gabriel R. Dosdos, Joel J. Orona, Daniel C. Nuez
  • Structure and method of testing failed or returned die to determine failure location and type
    Patent number: 6433360
    Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed from necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: August 13, 2002
    Assignee: Xilinx, Inc.
    Inventors: S. Gabriel R. Dosdos, Joel J. Orona, Daniel C. Nuez