Patents by Inventor Joel Jeremiah Guevarra Atienza

Joel Jeremiah Guevarra Atienza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736103
    Abstract: A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 22, 2023
    Assignee: Appleton Grp LLC
    Inventors: Joel Jeremiah Guevarra Atienza, Mark Chester Bernardino Nepomuceno, Jonathan Art Fulgencio Recaflanca, Runelle Namoro Tria
  • Publication number: 20220407509
    Abstract: A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Joel Jeremiah Guevarra Atienza, Mark Chester Bernardino Nepomuceno, Jonathan Art Fulgencio Recaflanca, Runelle Namoro Tria
  • Patent number: 11522356
    Abstract: A power supply comprises voltage regulation circuitry, a load-share controller, and overcurrent protection circuitry. The voltage regulation circuitry is configured to output a regulated voltage. The load-share controller is configured to control the voltage regulation circuitry to adjust the regulated voltage responsive to a load-share voltage signal (LSV) that indicates an amount of load current being delivered to a load. The overcurrent protection circuitry is configured to selectively couple the regulated voltage to the load. When the load current exceeds a threshold current, the overcurrent protection circuitry is configured to decouple the regulated voltage from the load. While the regulated voltage is decoupled from the load, and when the LSV signal indicates that load current is being delivered to the load by a different power supply, the overcurrent protection circuitry is configured to recouple the regulated voltage to the load.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 6, 2022
    Assignee: Appleton Grp LLC
    Inventors: Joel Jeremiah Guevarra Atienza, John Rommel Baduel De Robles, Mark Chester Bernardino Nepomuceno