Patents by Inventor Joel Zvi Apisdorf
Joel Zvi Apisdorf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134216Abstract: The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.Type: ApplicationFiled: December 15, 2023Publication date: April 25, 2024Inventors: Joel Zvi APISDORF, jAMES mICHAEL WILLIAMS, Phillip Douglas SOLOMON, Jason Madjdi AMINI
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Patent number: 11899292Abstract: The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.Type: GrantFiled: May 6, 2022Date of Patent: February 13, 2024Assignee: IonQ, Inc.Inventors: Joel Zvi Apisdorf, James Michael Williams, Phillip Douglas Solomon, Jason Madjdi Amini
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Publication number: 20220260860Abstract: The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Joel Zvi APISDORF, James Michael WILLIAMS, Phillip Douglas SOLOMON, Jason Madjdi AMINI
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Patent number: 11402671Abstract: The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.Type: GrantFiled: July 23, 2020Date of Patent: August 2, 2022Assignee: IONQ, INC.Inventors: Joel Zvi Apisdorf, James Michael Williams, Phillip Douglas Solomon, Jason Madjdi Amini
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Publication number: 20210026162Abstract: The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.Type: ApplicationFiled: July 23, 2020Publication date: January 28, 2021Inventors: Joel Zvi APISDORF, James Michael WILLIAMS, Phillip Douglas SOLOMON, Jason Madjdi AMINI
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Patent number: 6978459Abstract: A system and method process data elements on multiple processing elements. A first processing element processes a task. A second processing element, coupled to the first processing element, is associated with a task. The first processing element sends a critical-section end signal to the second processing element while processing the task at the first processing element. The second processing element resumes the task in response to receiving the critical-section end signal.Type: GrantFiled: April 13, 2001Date of Patent: December 20, 2005Assignee: The United States of America as represented by the Secretary of the NavyInventors: Jack Bonnell Dennis, Joel Zvi Apisdorf, Sam Brandon Sandbote
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Patent number: 6968447Abstract: A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.Type: GrantFiled: April 13, 2001Date of Patent: November 22, 2005Assignee: The United States of America as represented by the Secretary of the NavyInventors: Joel Zvi Apisdorf, Sam Brandon Sandbote, Michael Daniel Poole
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Patent number: 6950927Abstract: A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.Type: GrantFiled: April 13, 2001Date of Patent: September 27, 2005Assignee: The United States of America as represented by the Secretary of the NavyInventors: Joel Zvi Apisdorf, Sam Brandon Sandbote
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Patent number: RE43825Abstract: A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.Type: GrantFiled: November 19, 2007Date of Patent: November 20, 2012Assignee: The United States of America as Represented by the Secretary of the NavyInventors: Joel Zvi Apisdorf, Sam Brandon Sandbote, Michael Daniel Poole
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Patent number: RE44129Abstract: A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.Type: GrantFiled: September 27, 2007Date of Patent: April 2, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Joel Zvi Apisdorf, Sam Brandon Sandbote, Michael Daniel Poole