Patents by Inventor Joerg Kayser
Joerg Kayser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9069574Abstract: A computer program product and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: GrantFiled: December 11, 2013Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
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Patent number: 9064074Abstract: According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.Type: GrantFiled: November 14, 2011Date of Patent: June 23, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Kayser, Helmut Kohler, Norbert Schumacher
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Patent number: 9015685Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: GrantFiled: March 1, 2013Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
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Publication number: 20140250429Abstract: A computer program product and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: ApplicationFiled: December 11, 2013Publication date: September 4, 2014Applicant: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
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Publication number: 20140250443Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
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Publication number: 20130124182Abstract: According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Kayser, Helmut Kohler, Norbert Schumacher
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Patent number: 6834359Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.Type: GrantFiled: September 21, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Harald Boehm, Joachim von Buttlar, Axel Horsch, Joerg Kayser, Stefan Koerner, Martin Kuenzel
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Publication number: 20020087917Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.Type: ApplicationFiled: September 21, 2001Publication date: July 4, 2002Applicant: International Business Machines CorporationInventors: Harald Boehm, Joachim von Buttlar, Axel Horsch, Joerg Kayser, Stefan Koerner, Martin Kuenzel