Patents by Inventor Joey G. Piamonte

Joey G. Piamonte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080003718
    Abstract: Methods are disclosed for singulating block-molded IC packages. The methods of the invention include steps for making a partial cut in a block-molded semiconductor array, the partial cut defining the perimeter of an IC package and extending partially through the thickness of the array material. In a subsequent step, a final cut is made in alignment with the partial cut at the perimeter of the package such that the package is severed from adjacent material. Various embodiments of the invention are disclosed, including methods for making a plurality of partial cuts prior to making the final cut severing the package from the array, making cuts approaching from the same surface of the array, and making cuts approaching from opposing surfaces of the array. The partial cutting steps are used to prevent array warpage and facilitate hold-down during ball attach and/or singulation processes.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Erwin Remoblas Estepa, Ronaldo Marasigan Arguelles, Jesus Bajo Bautista, Joey G. Piamonte