Patents by Inventor Joezac John Zachariah

Joezac John Zachariah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated debugging method for over-constrained circuit verification environment
    Patent number: 8104001
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: January 24, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
  • Method for providing information associated with an over-constrained event in verification of a circuit design
    Patent number: 8099696
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: January 17, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
  • Automated debugging method and system for over-constrained circuit verification environment
    Patent number: 8099695
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: January 17, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
  • Method for checking a status of a signal port to identify an over-constrained event
    Patent number: 7984401
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: July 19, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
  • AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
    Publication number: 20090144680
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 4, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amir LEHAVOT, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer
  • AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
    Publication number: 20090144681
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 4, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amir LEHAVOT, Vinaya Kumar SINGH, Joezac John ZACHARIAH, Jose BARANDIARAN, Axel Siegfried SCHERER
  • AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
    Publication number: 20090144683
    Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 4, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer