Abstract: Systems and methods related to serial communication devices are provided. An example integrated circuit (IC) device includes interface circuitry coupled to a two-wire serial communication bus having a serial clock (SCL) line and a serial data (SDA) bus line. The IC device further includes bus stuck recovery circuitry to monitor for a local SDA fault condition at the IC device based on a number of clock cycles during which an internal SDA signal (e.g., generated by the IC device) drives the SDA bus line to a first signal state, the clock cycles based on a clock signal received from the SCL line; and responsive to the local SDA fault condition, release the SDA bus line independent of the internal SDA signal, where the SDA bus line is in a second signal state different from the first signal state based on the release.

Abstract: A multiple impedance string, multiple output digital-to-analog converter (DAC) circuit that can include a shared coarse resolution DAC, two first fine resolution DACs to receive outputs of the MSB DAC, and a multiplexer to multiplex outputs of the first and second fine resolution DACs to output terminals. The multiplexer can be configured to interchange coupling of the outputs of the first and second fine resolution DACs using one or more MSBs.

Abstract: A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.

Abstract: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.