Patents by Inventor Johan Weijtmans

Johan Weijtmans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8835263
    Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Johan Weijtmans, Jiong-Ping Lu, Rick Wise
  • Publication number: 20100038727
    Abstract: A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions.
    Type: Application
    Filed: October 21, 2009
    Publication date: February 18, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram, Johan Weijtmans
  • Publication number: 20090179236
    Abstract: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
    Type: Application
    Filed: March 19, 2009
    Publication date: July 16, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram, Johan Weijtmans
  • Patent number: 7553717
    Abstract: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: June 30, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram, Johan Weijtmans
  • Publication number: 20080277699
    Abstract: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram, Johan Weijtmans
  • Publication number: 20080242032
    Abstract: A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram, Johan Weijtmans
  • Publication number: 20080199999
    Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 21, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Johan Weijtmans, Jiong-Ping Lu, Rick Wise