Abstract: The present invention relates to a particle-optical component comprising a first multi-aperture plate, and a second multi-aperture plate forming a gap between them; wherein a plurality of apertures of the first multi-aperture plate is arranged such that each aperture of the plurality of apertures of the first multi-aperture plate is aligned with a corresponding aperture of a plurality of apertures of the second multi-aperture plate; and wherein the gap has a first width at a first location and a second width at a second location and wherein the second width is by at least 5% greater than the first width. In addition, the present invention pertains to charged particle systems and arrangements comprising such components and methods of manufacturing multi aperture plates having a curved surface.

Abstract: The present invention relates to a particle-optical component comprising a first multi-aperture plate, and a second multi-aperture plate forming a gap between them; wherein a plurality of apertures of the first multi-aperture plate is arranged such that each aperture of the plurality of apertures of the first multi-aperture plate is aligned with a corresponding aperture of a plurality of apertures of the second multi-aperture plate; and wherein the gap has a first width at a first location and a second width at a second location and wherein the second width is by at least 5% greater than the first width. In addition, the present invention pertains to charged particle systems and arrangements comprising such components and methods of manufacturing multi aperture plates having a curved surface.

Abstract: The invention relates to a contact probe arrangement for electrically connecting a test system with contact pads of a device to be tested. The contact probes are located in guide grooves. The guide grooves as well as areas are provided in a plane parallel to the surface of a guide plate and are covered by a protective plate. The contact probes may bend out laterally into the respective areas. This assures a very dense contact probe array. Contact probe arrays of this type may be used, for example, for detecting opens and shorts in integrated circuits or semiconductor chips. The invention overcomes the problem of adjusting for height differences in the contact pads caused by an uneven surface of the device to be tested.

Abstract: The invention relates to a contact probe arrangement for electrically connecting a test system with contact pads of a device to be tested. The contact probes are located in guide grooves. The guide grooves as well as areas are provided in a plane parallel to the surface of a guide plate and are covered by a protective plate. The contact probes may bend out laterally into the respective areas. This assures a very dense contact probe array. Contact probe arrays of this type may be used, for example, for detecting opens and shorts in integrated circuits or semiconductor chips. The invention overcomes the problem of adjusting for height differences in the contact pads caused by an uneven surface of the device to be tested.

Abstract: A calibration standard comprises a supporting structure (1) of single crystal material with at least one pair of different kinds of structures consisting of a raised line (2) and a trench (3). These structures have the identical width in the range of about 500 nm. The single crystal material preferably is silicon with (110)-orientation.

Abstract: The invention pertains to a micromechanical sensor for AFM/STM profilometry which consists of a beam with a point for interaction with a test surface to be sampled on one end and a fixing block on the other end. The point consists of a basically conical shank with a countersunk point at the end of the shank. The micromechanical sensor has excellent mechanical rigidity and is particularly suited to the measurement of extremely deep and narrow structures with positive side flank angles.

Abstract: A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m<G.ltoreq.100 .mu.m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Abstract: A micromechanically fabricated read/write head for charge storage devices comprising a supporting base, a cantilever and a tip with a shaft and frontside end. The supporting base, cantilever and tip form one integral part made of electrically conducting material. The frontside end of the tip is so designed as to allow writing and reading of information in direct contact with the surface of a charge storage device. The shaft of the tip has a small diameter and is surrounded by a strengthening shell.

Abstract: An ion generator for the generation of a plasma is assembled from module subassemblies. The first subassembly includes a dielectric plate 1, on the first surface 1a of which are located a large number of first electrodes 3, and the second surface 1b of which is coated with a structured conductive layer 2. The second subassembly includes an aperatured spacer plate with a large number of dielectric spacers with a second electrode 5 on the side facing away from the dielectric plate 1. In joining the subassemblies together, the aperatured spacer plate is connected to the dielectric plate 1 at its first surface 1a in such a way that cavities 6 for accommodating plasma are formed by the first electrodes 3, parts of the first surface 1a of the dielectric plate 1 and the spacers 4 with the second electrodes 5. The first set of electrodes 3 shield the points where the subassemblies are bonded together from plasma in the cavities.

Abstract: The invention relates to calibration standards which are used chiefly for the calibration of profilometers and in atomic force- and scanning probe microscopes. The calibration standard has one step of defined height H or a multi-step system formed of several steps of the same step-height H and consisting of exactly one material. The manufacturing procedure for the calibration standard requires only a single masking layer for each of the different versions in the form of a one-step standard or a multi-step system.

Abstract: Membrane masks for electron-beam lithography are described which have a high mechanical stability and low membrane thickness, are free of stress and the submicron structures of which are easy to produce using reactive ion etching methods without rounding effects.In the case of a membrane mask for structuring surface areas with the aid of electron or corpuscular beams, a layer 1 of silicon nitride with going right through openings, which define the mask pattern, is deposited on one surface of a semiconductor wafer 2, which consists preferably of silicon. A tub-shaped recess 3 extends from the other surface of the semiconductor wafer 2 as far as the layer-carrying surface.A further mask for structuring surface areas with the aid of electron beams has at least one continuous layer 30 and a layer 31 defining the mask pattern.These two layers are deposited on the surface of a semiconductor wafer 32 with a tub-shaped recess 33.

Abstract: An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m<G.ltoreq.approximately 100 .mu.m. A metallic interconnect is disposed over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

Abstract: A calibration standard comprises a supporting structure (1) of single crystal material with at least one pair of different kinds of structures consisting of a raised line (2) and a trench (3). These structures have the identical width in the range of about 500 nm. The single crystal material preferably is silicon with (110)-orientation.

Abstract: A contact probe arrangement for electrical functional testing, including a first stack of perforated plates, a second stack of perforated plates and a plurality of contact probes. The probes are in contact with the second stack of perforated plates, and in communication with the first stack, the probes are arranged and dimensioned such that the probes are capable of lateral buckling and capable of being guided through the first stack. The contact probe arrangement also includes a test card, a counterholding piece attached to the test card, and a pressure plate, the pressure plate movably connected to the test card. The first perforated plate is connected to the second perforated plate such that the first perforated plate is capable of movement toward and away from the second perforated plate and the second perforated plate is connected to the first perforated plate such that the second perforated plate is capable of movement toward and away from the first perforated plate.

Abstract: The invention relates to a manufacturing method for a membrane mask suitable for particle beams with mask fields, which are bounded by thin support walls.The deep plasma etching for the formation of the support walls is halted shortly before reaching the membrane and the last .mu.m before the membrane removed by wet-chemical etching. A high etch selectivity can be achieved using an alkaline etching solution.The support walls 1 are turned by 45.degree. to the (110) direction or oriented parallel to the (100) plane, so that the structures restricted by (111) planes are avoided.

Abstract: Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

Abstract: The invention relates to an adhesive bond 1 for a plurality of densely packed elements 4a, 4b, 4c guided into a plate pack 3. At the plate surface 2 with the adhesive bond 1 the guidance holes 5a are made larger than the guidance holes 5b in the remainder of the plate pack (3) and the adhesive bond is effected by means of a highly viscous adhesive. Because of the larger opening 5a, an adhesive reservoir 10 is formed at the plate surface 2. This makes it possible to use high viscosity adhesives. The geometric features and the use of a highly viscous adhesive make it possible to manufacture durable and heat-resistant adhesive bonds for elements such as wires, glass fibers or micromechanical components.

Abstract: Disclosed is a reproducible process for making an SiO.sub.2 layer by thermal oxidation which assures an extremely uniform thickness of the SiO.sub.2 layer of approximately 1%. The process of the invention comprises the steps growing an initial layer of SiO.sub.2 to a defined minimal thickness by dry oxidation and increasing the thickness of the initial layer by simultaneous wet and dry oxidation until the desired final thickness is reached.

Abstract: The invention generally relates to the technical field of devices using the effect to emit electrons out of a solid into vacuum due to high electric field strength. Such devices are usually called field emission devices. The invention relates more specifically to the structure of a field emission device, to the method of fabricating a field emission device, and to the use of a multitude of field emission devices in the technical field of flat panel displays. The inventive structure of a field emission device (15) comprises an individual series resistor for each electron emitting tip (1), wherein the series resistor is formed by the tip (1) itself. The tip (1) comprises a body (9) of a first material with high resistivity and an at least partial coating (7) of a second material with low work function, wherein the body (9) of the first material forms the series resistor and the coating (7) of the second material provides for electron emission.

Abstract: An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.