Patents by Inventor Johanna M. Swan
Johanna M. Swan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876053Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).Type: GrantFiled: January 7, 2021Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
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Publication number: 20230395518Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: Intel CorporationInventors: Aleksandar Aleksov, Johanna M. Swan
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Patent number: 11830787Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.Type: GrantFiled: August 6, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
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Patent number: 11824008Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).Type: GrantFiled: September 29, 2022Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
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Publication number: 20230369236Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Publication number: 20230343716Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Applicant: Intel CorporationInventors: Adel A. ELSHERBINI, Amr ELSHAZLY, Arun CHANDRASEKHAR, Shawna M. LIFF, Johanna M. SWAN
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Patent number: 11791277Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: GrantFiled: April 8, 2022Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11784181Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.Type: GrantFiled: January 21, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
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Patent number: 11784108Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.Type: GrantFiled: August 6, 2019Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
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Publication number: 20230320021Abstract: Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Applicant: Intel CorporationInventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
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Patent number: 11776869Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.Type: GrantFiled: April 11, 2022Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
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Patent number: 11769751Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a transmitter/receiver logic (TRL) die coupled to the first surface of the package substrate; a plurality of antenna elements adjacent the second surface of the package substrate; and a transmitter/receiver chain (TRC) die, wherein the TRC die is embedded in the package substrate, and wherein the TRC die is electrically coupled to the RF die and at least one of the plurality of antenna elements via conductive pathways in the package substrate. In some embodiments, a microelectronic assembly may further include a double-sided TRC die. In some embodiments, a microelectronic assembly may further include a TRC die having an amplifier. In some embodiments, a microelectronic assembly may further include a TRL die having a modem and a phase shifter.Type: GrantFiled: December 29, 2017Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan
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Patent number: 11769734Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.Type: GrantFiled: March 23, 2022Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Johanna M. Swan
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Patent number: 11764452Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.Type: GrantFiled: February 16, 2022Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
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Patent number: 11756943Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die.Type: GrantFiled: December 29, 2017Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11749628Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.Type: GrantFiled: November 9, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Lift, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
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Patent number: 11751367Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.Type: GrantFiled: September 7, 2021Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
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Patent number: 11749642Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: March 28, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Patent number: 11728290Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.Type: GrantFiled: April 25, 2019Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Georgios Dogiamis, Johanna M. Swan, Aleksandar Aleksov, Telesphor Kamgaing, Henning Braunisch
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Patent number: 11721649Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.Type: GrantFiled: May 19, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Kimin Jun, Brennen Mueller, Shawna M. Liff, Johanna M. Swan, Paul B. Fischer