Patents by Inventor Johanna M. Swan

Johanna M. Swan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microelectronic assemblies with communication networks
    Patent number: 11342305
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Lift, Johanna M. Swan
  • Microelectronic assemblies
    Patent number: 11335642
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
  • Microelectronic assemblies
    Patent number: 11335665
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
  • Microelectronic assemblies
    Patent number: 11335641
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Microelectronic assemblies
    Patent number: 11335663
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Fast-lane routing for multi-chip packages
    Patent number: 11336559
    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Tejpal Singh, Shawna M. Liff, Gerald S. Pasdast, Johanna M. Swan
  • DIE BACKEND DIODES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    Publication number: 20220149036
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Package with a highly conductive layer deposited on die using throughput additive deposition prior to TIM1 dispense
    Patent number: 11328978
    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Sergio Chan Arguedas, John J. Beatty
  • Capacitor-wirebond pad structures for integrated circuit packages
    Patent number: 11328986
    Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Georgios Dogiamis, Telesphor Kamgaing, Johanna M. Swan
  • Substrate integrated posts and heat spreader customization for enhanced package thermomechanics
    Patent number: 11328979
    Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Dinesh Padmanabhan Ramalekshmi Thanu, Sergio Chan Arguedas, Johanna M. Swan, John J. Beatty
  • Dielectric waveguide including a dielectric material with cavities therein surrounded by a conductive coating forming a wall for the cavities
    Patent number: 11329359
    Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
  • Multi-filter die
    Patent number: 11316497
    Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Microelectronic package with substrate-integrated components
    Patent number: 11310907
    Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Microelectronic assemblies having substrate-integrated perovskite layers
    Patent number: 11302618
    Abstract: Disclosed herein are microelectronic assemblies with integrated perovskite layers, and related devices and methods. For example, in some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, and a perovskite conductive layer on the conductive layer. In some embodiments, a microelectronic assembly may include an organic package substrate portion having a surface with a conductive layer, a perovskite conductive layer having a first crystalline structure on the conductive layer, and a perovskite dielectric layer having a second crystalline structure on the perovskite conductive layer. In some embodiments, the first and second crystalline structures have a same orientation.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff, Thomas Sounart, Johanna M. Swan
  • Electrostatic discharge protection in integrated circuits
    Patent number: 11296040
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • TSV-less die stacking using plated pillars/through mold interconnect
    Patent number: 11296052
    Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Preston T. Meyers, Javier A. Falcon, Shawna M. Liff, Joe R. Saucedo, Adel A. Elsherbini, Albert S. Lopez, Johanna M. Swan
  • GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY
    Publication number: 20220102339
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY
    Publication number: 20220102344
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • CONDUCTIVE CONTACT STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS
    Publication number: 20220102270
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Electrostatic discharge protection in integrated circuits using materials with optically controlled electrical conductivity
    Patent number: 11289431
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan