Patents by Inventor Johannes Hermanus Aloysius De Rijk
Johannes Hermanus Aloysius De Rijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9595972Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.Type: GrantFiled: March 9, 2016Date of Patent: March 14, 2017Assignee: Microsemi Semiconductor ULCInventors: Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Paul H. L. M. Schram, Mark A Warriner
-
Publication number: 20160301416Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.Type: ApplicationFiled: March 9, 2016Publication date: October 13, 2016Inventors: Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Paul H.L.M. Schram, Mark A. Warriner
-
Patent number: 7728634Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.Type: GrantFiled: July 25, 2008Date of Patent: June 1, 2010Assignee: Zarlink Semiconductor Inc.Inventors: Johannes Hermanus Aloysius De Rijk, Robertus Laurentius van der Valk
-
Patent number: 7642862Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.Type: GrantFiled: November 14, 2007Date of Patent: January 5, 2010Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paul Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
-
Publication number: 20090184736Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.Type: ApplicationFiled: July 25, 2008Publication date: July 23, 2009Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Johannes Hermanus Aloysius De Rijk, Robertus Laurentius van der Valk
-
Patent number: 7557624Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.Type: GrantFiled: November 15, 2007Date of Patent: July 7, 2009Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
-
Publication number: 20080122504Abstract: A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.Type: ApplicationFiled: November 15, 2007Publication date: May 29, 2008Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
-
Publication number: 20080116982Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.Type: ApplicationFiled: November 14, 2007Publication date: May 22, 2008Applicant: ZARLINK SEMICONDUCTOR INC.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
-
Patent number: 7096243Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.Type: GrantFiled: January 21, 2003Date of Patent: August 22, 2006Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
-
Patent number: 6784706Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The method includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.Type: GrantFiled: December 20, 2002Date of Patent: August 31, 2004Assignee: Zarlink Semiconductor, Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius de Rijk
-
Publication number: 20030177156Abstract: A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.Type: ApplicationFiled: January 21, 2003Publication date: September 18, 2003Applicant: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
-
Publication number: 20030137329Abstract: The method is capable of rapidly bringing a phase-locked loop subject to overshoot into lock after a phase or frequency jump. The phase-locked loop has a phase detector, a controlled oscillator, and an integrator having an output frequency setting that, with the output of said phase detector, determines a frequency setting of the controlled oscillator. The includes the steps of storing a value for the output frequency setting of the integrator prior to the phase or frequency jump, determining when a phase hit occurs after the phase or frequency jump, and restoring the output frequency setting of the integrator to the stored value on or soon after the phase hit to reduce overshoot. In this way the degradation of PLL performance is minimized.Type: ApplicationFiled: December 20, 2002Publication date: July 24, 2003Applicant: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk