Abstract: A pixel includes an array of a plurality of photodiodes. The array of photodiodes includes a plurality of rows of photodiodes and a plurality of columns of photodiodes. The plurality of photodiodes includes a set of first photodiodes that has a first surface area and at least one second photodiode that has a second surface area that is smaller than the first surface area. The first photodiodes are arranged to be symmetric with respect to the at least one second photodiode. Output circuitry is electrically coupled to each of the first photodiodes in the set of first photodiodes. A switch is selectively, operably closed to electrically couple the output circuitry to the second photodiode.

Abstract: A pixel includes an array of a plurality of photodiodes. The array of photodiodes includes a plurality of rows of photodiodes and a plurality of columns of photodiodes. The plurality of photodiodes includes a set of first photodiodes that has a first surface area and at least one second photodiode that has a second surface area that is smaller than the first surface area. The first photodiodes are arranged to be symmetric with respect to the at least one second photodiode. Output circuitry is electrically coupled to each of the first photodiodes in the set of first photodiodes. A switch is selectively, operably closed to electrically couple the output circuitry to the second photodiode.

Abstract: Apparatuses and methods for a skimming photodiode with high dynamic range (HDR) and reduced Light Emitting Diode (LED) flicker in imaging system are disclosed herein. A voltage generator provides a transfer gate voltage to a transfer transistor. The transfer gate voltage is a voltage selected one of a transfer-on, a transfer-off, and a skimming voltage. The transfer transistor transfers charges generated on a Complementary Metal-Oxide-Semiconductor (CMOS) photodiode (PD) to a floating diffusion (FD). The voltage on transfer gate controls the amount of the charges that can be transferred from the PD to the FD. A reset transistor precharges the PD and FD to an AVDD. A first enable transistor controls the amount of charges transferred from the FD to a first capacitor. A second enable transistor controls the amount of charges transferred from the FD to a second capacitor. The first and second enable transistors receive their individual periodical control pulses once activated.

Abstract: An image sensor for detecting light-emitting diode (LED) without flickering includes a pixel array with pixels. Each pixel including subpixels including a first and a second subpixel, dual floating diffusion (DFD) transistor, and a capacitor coupled to the DFD transistor. First subpixel includes a first photosensitive element to acquire a first image charge, and a first transfer gate transistor to selectively transfer the first image charge from the first photosensitive element to a first floating diffusion (FD) node. Second subpixel includes a second photosensitive element to acquire a second image charge, and a second transfer gate transistor to selectively transfer the second image charge from the second photosensitive element to a second FD node. DFD transistor coupled to the first and the second FD nodes. Other embodiments are also described.

Abstract: Apparatuses and methods for image sensors with pixels that reduce or eliminate flicker induced by high intensity illumination are disclosed. An example image sensor may include a photodiode, a transfer gate, an anti-blooming gate, and first and second source follower transistors. The photodiode may capture light and generate charge in response, and the photodiode may have a charge capacity. The transfer gate may selectively transfer charge to a first floating diffusion, and the anti-blooming gate may selectively transfer excess charge to a second floating diffusion when the generated charge is greater than the photodiode charge capacity.

Abstract: Apparatuses and methods for image sensors with pixels that reduce or eliminate flicker induced by high intensity illumination are disclosed. An example image sensor may include a photodiode, a transfer gate, an anti-blooming gate, and first and second source follower transistors. The photodiode may capture light and generate charge in response, and the photodiode may have a charge capacity. The transfer gate may selectively transfer charge to a first floating diffusion, and the anti-blooming gate may selectively transfer excess charge to a second floating diffusion when the generated charge is greater than the photodiode charge capacity.

Abstract: An image sensor for detecting light-emitting diode (LED) without flickering includes a pixel array with pixels. Each pixel including subpixels including a first and a second subpixel, dual floating diffusion (DFD) transistor, and a capacitor coupled to the DFD transistor. First subpixel includes a first photosensitive element to acquire a first image charge, and a first transfer gate transistor to selectively transfer the first image charge from the first photosensitive element to a first floating diffusion (FD) node. Second subpixel includes a second photosensitive element to acquire a second image charge, and a second transfer gate transistor to selectively transfer the second image charge from the second photosensitive element to a second FD node. DFD transistor coupled to the first and the second FD nodes. Other embodiments are also described.

Abstract: Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.

Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, control circuitry and storage and processing circuitry. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive. The stacked-chip image sensor may be configured to capture image frames at a capture frame rate and to output processed image frames at an output frame rate that is lower that the capture frame rate. The storage and processing circuitry may be configured to process image frames concurrently with image capture operations. Processing image frames concurrently with image capture operations may include adjusting the positions of moving objects and by adjusting the pixel brightness values of regions of image frames that have changing brightness.

Abstract: An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.

Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Abstract: Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.

Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Abstract: Embodiments of an apparatus including a pixel array including a plurality of individual pixels grouped into pixel kernels having two or more individual pixels, wherein each pixel kernel includes a floating diffusion electrically coupled to all individual pixels in the kernel. A color filter array (CFA) is positioned over and optically coupled to the pixel array, the CFA comprising a plurality of tiled minimal repeating units, each including a plurality of scaled filters having a photoresponse selected from among two or more different photoresponses. Individual pixels within each pixel kernel are optically coupled to a scaled filter.

Abstract: A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.

Abstract: A method of reading out a pixel includes resetting a photodetector of the pixel. Light incident on the photodetector is then integrated for a single exposure of a single image capture. A floating diffusion node of the pixel is then reset. The floating diffusion is set to low conversion gain and a low conversion gain reset signal is sampled from the floating diffusion node. The floating diffusion is set to high conversion gain and a high conversion gain reset signal is sampled from the floating diffusion node. Charge carriers are transferred from the photodetector to the floating diffusion node and a high conversion image signal is then sampled from the floating diffusion node. The floating diffusion is set to low conversion gain. Charge carriers are transferred again from the photodetector to the floating diffusion node and a low conversion image signal is sampled from the floating diffusion node.

Abstract: A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.

Abstract: An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to-digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.

Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, control circuitry and storage and processing circuitry. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive. The stacked-chip image sensor may be configured to capture image frames at a capture frame rate and to output processed image frames at an output frame rate that is lower that the capture frame rate. The storage and processing circuitry may be configured to process image frames concurrently with image capture operations. Processing image frames concurrently with image capture operations may include adjusting the positions of moving objects and by adjusting the pixel brightness values of regions of image frames that have changing brightness.

Abstract: Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.