Abstract: A two-way network interface is provided for both sending transmission messages and receiving reception messages between a pair of processors through a network. The network interface uses transmission messages to transmit both data and information representing respective amounts of unreported buffer space R for receiving data items from reception messages in a buffer storage circuit. The network interface holds up transmission until a number A of data items, that a particular one of the data processing circuits has made available for transmission in the message and for which buffer space is available across the network, exceeds a threshold. However the threshold is lowered, or the transmission message is transmitted before the threshold is exceeded in response to an increase in the amount R of unreported available buffer space in the buffer storage circuit for the particular one of the processing circuits.

Abstract: An integrated circuit having a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a packet based communication based on transactions between said plurality of processing modules (M, S) is provided. Each packet comprises a first predetermined number of subsequent words each having a second predetermined number of bits. A first of said plurality of processing modules (M) issues a transaction by sending at least one packet over said interconnect means (N) to a second of said plurality of processing modules (S). The integrated circuit further comprises at least one packet inspecting unit (PIU) for inspecting bits of said at least one packet to determine bits not required for said issued transaction and for matching said not required bits of said at least one inspected packet with other bits of the same packet.

Abstract: The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising at least one SISO decoding unit (17, 21) for SISO decoding of the received information symbols (r) of a window, wherein a stopping criterion is applied to each window. This allows to abort iterative decoding for each window individually once convergence of decoding is determined by marking a window or sub-block inactive (17,23). An inactive window is no longer SISO decoded in subsequent iterations.

Abstract: A decoding method for decoding Low-Density Parity Check codes in transmission and recording systems includes a running minimum loop with the following iterative acts: reading a reliability value from the input sequence of input reliability values; comparing the reliability value with a stored value; and overwriting the stored value with the reliability value if the reliability value is smaller than the stored value.

Abstract: A turbo decoder system (1) for decoding turbo coded bits, is provided with a system input (2) and a plurality of turbo decoders (3; 3-1, . . . 3-n) each having a turbo decoder input (4; 4-1, . . . 4-n). The plurality of turbo decoders (3; 3-1, . . . 3-n) is arranged in parallel, and the system (1) is further provided with an allocating device (6) coupled between the system input (2) and the turbo decoder inputs (4; 4-1, . . . 4-n) for dynamically allocating the turbo coded bits to one of the turbo decoders (3; 3-1, . . . 3n).

Abstract: A turbo decoder employing the sliding window algorithm is computational intensive. Computational requirements are reduced in iterative decoders, at the expense of increased memory usage, by storing the stakes between iterations. The stakes used in this improved sliding windows algorithm can be compressed, resulting in a decoder with minimal additional memory requirements, while retaining the advantages in computational requirements obtained from storing the stakes between iterations.

Abstract: A turbo decoder system (1) for decoding turbo coded bits, is provided with a system input (2) and a plurality of turbo decoders (3; 3-1, . . . 3-n) each having a turbo decoder input (4; 4-1, . . . 4-n). The plurality of turbo decoders (3; 3-1, . . . 3-n) is arranged in parallel, and the system (1) is further provided with an allocating device (6) coupled between the system input (2) and the turbo decoder inputs (4; 4-1, . . . 4-n) for dynamically allocating the turbo coded bits to one of the turbo decoders (3; 3-1, . . . 3-n).

Abstract: A turbo decoder employing the sliding window algorithm is computational intensive. Recent developments have reduced the computational requirements in iterative decoders at the expense of increased memory usage by storing the stakes between iterations. The stakes used in this improved sliding windows algorithm can be compressed, resulting in a decoder with minimal additional memory requirements while retaining the advantages in computational requirements obtained from storing the stakes between iterations.