Abstract: A virtual address and access protection code stored at that address are fetched simultaneously from secondary memory and stored in corresponding locations in first and second content addressable memories. When a program-generated virtual address is later applied to the first content addressable memory, corresponding access code is simultaneously applied to the second content addressable memory. Match signals obtained simultaneously from corresponding locations in both content addressable memories are combined to produce an access control signal to control access to data stored at a real memory address corresponding to the matched virtual address.

Abstract: This apparatus is used for minimizing the performance degradation due to address translation in computer systems employing random access memory and paging. It translates initial addresses into real addresses utilizing addressable memory and substitute paging. It decreases access time by not translating virtual address bits that are also real address bits and by commencing memory access using the available real address bits as they are available.

Abstract: A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.