Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source.

Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source.

Abstract: An integrated circuit biasing network for producing .a.predetermined level of bias current. The bias network includes a field-effect transistor having a gate, a source and a drain. The transistor produces a level of bias current corresponding to a predetermined input gate-source voltage applied to the field effect transistor. A control circuit is provided. The control circuit is connected to the field effect transistor and provides a current through a control current path to produce the field effect transistor input voltage. A compensation circuit is connected to the control circuit. The compensation circuit includes a compensation transistor of the same type as the field effect transistor.

Abstract: An amplifier having a two different single crystal semiconductor substrates. A first one of the substrates has formed thereon at least one input signal amplifying device, such device comprising a bipolar transistor. A second one of the substrates is a material different from the material of the first substrate. A current mirror is included. The current mirror includes a plurality of electrically interconnected active devices, one portion of the devices being bipolar devices formed on the first substrate and another portion of the active devices comprising an insulated gate field effect transistor formed on the second substrate. The first single crystal substrate is III-V material and the second single crystal substrate is silicon. The bipolar devices are HBTs. The insulated gate field effect transistor is a MOS device. This configuration minimizes the effect of temperature, voltage and process variations on critical transistor operating currents.

Abstract: A synchronous latch device macrocell which includes an input gate section and a scannable latch section. Both sections are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits. The non-inverting output of the latch section connects to an output pin and provides a signal representation of the state of the latch device. The output pin is externally connected through a conductor wire to either one of a pair of complementary data input pins of the input gate section. The connection made is selected as a function of which data input pin connection provides the faster loading of the latch device as viewed from the source of the signal applied to the load control pin of the input gate section.

Abstract: Apparatus adjusts the low supply voltage applied to the bipolar gate array circuits of a semiconductor chip to provide uniform propagation delay in the signals operated on by the array circuits notwithstanding variations in manufacturing tolerances and temperature variations. The apparatus includes a voltage regulator circuit and a first resistor located off the chip connected between its output and adjustment terminals and a second resistor located on the chip connected to the adjustment terminal of the regulator circuit. The voltage regulator circuit in response to changes in the resistance of the second resistor adjusts the low supply voltage at its output terminal so as to provide uniform signal delays through the array circuits.