Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: A improved method and system for regenerating a video pixel and/or audio sampling clock in a system that wirelessly transfers video and audio content from a content source to a content sink.

Abstract: The present invention provides systems for improved quality of service and traffic management in network routers and other devices. This is achieved, according to one aspect of the invention, by coupling a plurality of queue processors to a plurality of input interfaces that receive data from one or more respective network connections. Each queue processor, in coordination with an associated scheduler that schedules dequeing of data from one or more queues, maintains the quality of service levels with respect to throughput, and delivers the data for a particular output context based on priority to a respective output interface. The output interface is coupled to the plurality of queue processors and transfers the data to one or more respective network connections. In addition, a plurality of output interfaces can be coupled to respective pluralities of queue processors for transferring data therefrom to one or more destination network connections.

Abstract: Quality of Service (“QoS”) variables for predetermined protocol Type data units are stored in a cache memory. For data units that are associated with a flow, thirteen bytes selected out of the Internet Protocol (“IP”) header are employed as at least a portion of a key to perform a cache lookup to obtain at least one Quality of Service variable from the cache. Both routing and QoS information may be stored in the cache for retrieval upon a single lookup operation.

Abstract: A Receive Frame Processor (RFP) in a network bridge/router for receiving frame-characterizing information from other elements of the bridge/router and for generating plural code vectors which result in the selective processing of a received frame in software and/or hardware is provided. The received information is utilized in constructing code vectors representative of how a received frame is to be processed. Further data structures stored in conjunction with the RFP are indexed by the constructed code vectors and indicate whether the frame is to be processed in the RFP hardware, by software in an associated Frame Processor, or both. These data structures also indicate whether the port through which the frame was received is to be blocked to prevent misordering of received frames. If the frame is to be processed in software, the RFP generates a Receive Vector which is provided to the FP and which conveys the frame-characterizing code vectors to the FP.

Abstract: A network bridge/router for identifying a data unit to be routed by a network bridge/router, for identifying a protocol associated with the received data unit to be routed, and for carrying out appropriate data unit transfer operations, all in hardware. A Receive Header Processor (RHP) analyzes the destination address of the received data unit, in hardware, for determining if routing or bridging is required. If routing is required, the RHP uses portions of the received data unit header as a compare value against predefined values stored in data structures which provide a protocol ID identifying the protocol of the received data unit and serving as an index to the appropriate microcode handling routine, executed by the RHP, for the data unit. The handling routine causes the RHP to forward data unit identifying information appropriate to the identified protocol and obtained from the received data unit to further hardware-based data unit processing elements.

Abstract: At least a portion of the data units in a bridge/router are processed by logic circuits according to cast type. The cast type, source address and destination address of an incoming data unit are determined by examining the header. For a unicast data unit, the source address and destination address are employed to obtain a transmit port indicator from memory, and the unicast data unit is directed to the port indicated by the transmit port indicator. For a non-unicast data unit, the source address and destination address are employed to obtain a first port mask that indicates valid ports for receipt of the data unit and a second port mask that indicates valid ports for transmission of the data unit from memory. The first and second port masks are combined to generate a third port mask, and the non-unicast data unit is directed to the ports indicated by the third port mask.

Abstract: At least a portion of the data units in a bridge/router device are analyzed for purposes of filtering by employing high speed logic circuits. A data unit is analyzed by such logic circuits by examining the header portion of the data unit, employing information obtained from the header portion to designate possible output ports for transmission of the data unit, examining a predefined per-port filter enable indicator to determine whether filtering is to be applied to the data unit, and applying filtering for each respective port for which the per-port filter enable indicator indicates that filtering is to be applied. Filtering is also implemented with logic circuits and executed at high speed. Filtering may be executed based on MAC address group, port group, combination MAC address and port group, protocol type, and non-unicast traffic frequency. Data units that cannot be analyzed by the logic circuits are analyzed by software.

Abstract: A method and apparatus is disclosed for translating data link layer and network layer frame headers at speeds approximating the reception rate of frames on respective communication links. High-speed header translation is achieved via the use of a dedicated microsequencer which identifies the receive frame encapsulation type and the transmit frame encapsulation type and based on such identification, selects a processing routine which is then executed to translate the frame header. The microsequencer is employed to control the movement of control information and frame header and payload information from an input FIFO, through the dedicated header processor, and to an output FIFO. The headers of the respective frames are translated within the dedicated header processor to facilitate header translation at high speeds. Via use of the presently disclosed header translation apparatus, layer 2 and layer 3 header translations, as well as other header translation functions may be rapidly performed.

Abstract: A method and cache management for a bridge or bridge/router providing high-speed, flexible address cache management. The unit maintains a network address cache and an age table, searches the cache for layer 2 and layer 3 addresses from received frame headers, and returns address search results. The unit includes an interface permitting processor manipulation of the cache and age table, and supports a 4-way set associative cache to store the network addresses. A plurality of functions implemented in hardware enables software manipulation of the associated cache. Four cache operating modes are selectable. The unit can identify and select destination ports within a Load Balanced Port Group for frame forwarding. The unit utilizes Virtual LAN identification in conjunction with a MAC address for lookup in the cache. A cyclic redundancy code for each address to be looked up in the cache is used as an index into the cache. If a cache thrash rate exceeds a predetermined threshold, CRC table values can be rewritten.

Abstract: Logic circuits are employed in a telecommunications bridge/router device to examine a received frame to determine which VLAN, if any, the frame is associated with. The protocol type, receive port identification, and receive VLAN tag are employed to determine the transmit port identification and transmit VLAN tag. A predefined table indicates which ports within the bridge/router are associated with the VLAN. The frame is excluded from transmission through the ports that are not associated with members of the respective the VLAN.

Abstract: A method and apparatus for increasing the throughput of a communications internetworking device. The method involves the generating, by internetworking device hardware, of a predetermined code vector in response to the current state of the communications internetworking device and information contained in a data packet received by the internetworking device. In response to the hardware generated predetermined code vector, a predetermined software routine is executed by a microprocessor in the internetworking device which controls how the data packet is to be transmitted to its destination. By using hardware to generate the code vector, time is saved over having software determine how the internetworking device is to handle the data packet.