Abstract: Data reduction for testing results obtained from the diagnostic testing of signal integrity at node points along a PC board using a Rank-of-Ranks data analysis methodology. The Rank-of-Ranks methodology including a reduction of node points along the PC board by the application of a node point reduction algorithm. Calculating a ratio of the Standard Deviation by the Mean for each node point and for each testing parameter to arrive at a Coefficient of Variation. Each node point is sorted and ranked based on the Coefficient of Variation for each tested parameter at a time. At each node point, Rank values of all the parameters are summed and then sorted on the basis of the Rank values. The node points are Re-ranked based on the sorted Rank values. The Re-ranked node points are entered into an ordered list or matrix where critical node points are chosen from the top of the Re-ranked node points for study, re-design and/or further testing of the PC board.

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract: A universal peripheral controller is disclosed which uses DMA devices to provide access between a plurality of peripheral devices and other circuits within a computer system. A processor in the computer system recognizes a request from the controller to connect a peripheral via the system bus to another circuit connected thereto and establishes the connection. The processor then passes information to the controller and leaves the task of controlling the transfer of information to the DMA circuitry in the controller. The controller has a sequencer which examines each of the plurality of peripherals connected to it in a round robin operation to determine which peripherals are requesting a connection via the computer system bus to transfer information. The sequencer limits the time each peripheral can be connected to the system bus before servicing another peripheral request in order that all peripherals have equal access to the system bus.

Abstract: In a computer system having at least a bus with at least one central processing unit (CPU), one random access memory (RAM), and a first configuration of a plurality of different types of peripheral units (e.g. tape drives, disk drives, diskette drives, printers, unit record peripherals, etc.) coupled to the bus, an apparatus for controlling the first configuration and also capable of controlling a predetermined number of other configurations of different types of peripheral units when any of that predetermined number of configurations of peripheral units is coupled to the bus.