Abstract: The disclosure herein describes deploying a Virtual Secure Enclave (VSE) using a universal enclave binary and a Trusted Runtime (TR). A universal enclave binary is generated that includes a set of binaries of Instruction Set Architectures (ISAs) associated with Trusted Execution Environment (TEE) hardware backends. A TEE hardware backend is identified in association with a VSE-compatible device. A VSE that is compatible with the identified TEE hardware backend is generated on the VSE-compatible device and an ISA binary that matches the TEE hardware backend is selected from the universal enclave binary. The selected binary is linked to a runtime library of the TR and loads the linked binary into memory of the generated VSE. The execution of a trusted application is initiated in the generated VSE using a set of interfaces of the TR. The trusted application depends on the TR interfaces rather than the selected ISA binary.

Abstract: A method for abrasive flow machining includes moving an abrasive media through a high-aspect passage of a workpiece. Local pressure of the abrasive media is increased at target abrasion surfaces of the high-aspect passage using a passage geometry that is configured to direct flow of the abrasive media into the target abrasion surfaces such that the target abrasion surfaces are preferentially polished by the abrasive media over other, non-targeted surfaces of the high-aspect passage at which the flow of the abrasive media is not directed into.

Abstract: An autonomous path treatment system and associated path treatment method uses a mobile path recording device having a locator, a processor and firmware to capture a sequence of coordinates and directions of travel of a path as the mobile device is moved along the path and generate a path program file. The system also has an autonomous path treatment robot having: a treatment mechanism for treating the path; a controller having a processor and memory storing firmware that when executed obeys steps of the path program file to control the motor and the treatment mechanism to treat the path; and a server configured to execute a path program to process the captured sequence of coordinates and directions into the path program file containing instructions for controlling the autonomous path treatment robot to treat the path based upon the coordinates.

Abstract: An autonomous path treatment system and associated path treatment method uses a mobile path recording device having a locator, a processor and firmware to capture a sequence of coordinates and directions of travel of a path as the mobile device is moved along the path and generate a path program file. The system also has an autonomous path treatment robot having: a treatment mechanism for treating the path; a controller having a processor and memory storing firmware that when executed obeys steps of the path program file to control the motor and the treatment mechanism to treat the path; and a server configured to execute a path program to process the captured sequence of coordinates and directions into the path program file containing instructions for controlling the autonomous path treatment robot to treat the path based upon the coordinates.

Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.

Abstract: One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion.

Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.

Abstract: An electrochemical device includes an enclosure formed over a structure and defining an area between vertical portions of the enclosure. An electrochemical channel structure includes an electrolyte formed within the area wherein the electrolyte is protected from exposure on sidewalls of the electrolyte by the enclosure.

Abstract: An electrochemical device includes an enclosure formed over a structure and defining an area between vertical portions of the enclosure. An electrochemical channel structure includes an electrolyte formed within the area wherein the electrolyte is protected from exposure on sidewalls of the electrolyte by the enclosure.

Abstract: A method for generating a report by a computing device is described. The method includes identifying a specific health care intervention. The method also includes creating a health care cohort for the specific health care intervention. The health care cohort includes a definition of a primary intervention. The method further includes generating a report based on the health care cohort.

Abstract: An ultra-small diameter and a tall bottom electrode for use in magnetic random access memory (MRAM) devices containing a multilayered MTJ pillar is provided. The bottom electrode is formed by depositing a thick bottom electrode layer on a surface of a metallic etch stop layer. The bottom electrode layer is then patterned by lithography and etching to provide a bottom electrode structure. An angled ion beam etch is thereafter used to trim the bottom electrode structure into a bottom electrode having a high aspect ratio (on the order of 10:1 or greater).

Abstract: An anode structure for rechargeable lithium-ion batteries that have a high-capacity are provided. The anode structure, which is made utilizing an anodic etching process, is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region 1) having a first thickness and a first porosity, and a bottom porous layer (Porous Region 2) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.

Abstract: An autonomous path treatment system and associated path treatment method uses a mobile path recording device having a locator, a processor and firmware to capture a sequence of coordinates and directions of travel of a path as the mobile device is moved along the path and generate a path program file. The system also has an autonomous path treatment robot having: a treatment mechanism for treating the path; a controller having a processor and memory storing firmware that when executed obeys steps of the path program file to control the motor and the treatment mechanism to treat the path; and a server configured to execute a path program to process the captured sequence of coordinates and directions into the path program file containing instructions for controlling the autonomous path treatment robot to treat the path based upon the coordinates.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: An ultra-small diameter and a tall bottom electrode for use in magnetic random access memory (MRAM) devices containing a multilayered MTJ pillar is provided. The bottom electrode is formed by depositing a thick bottom electrode layer on a surface of a metallic etch stop layer. The bottom electrode layer is then patterned by lithography and etching to provide a bottom electrode structure. An angled ion beam etch is thereafter used to trim the bottom electrode structure into a bottom electrode having a high aspect ratio (on the order of 10:1 or greater).

Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.

Abstract: An anode structure for rechargeable lithium-ion batteries that have a high-capacity are provided. The anode structure, which is made utilizing an anodic etching process, is of unitary construction and includes a non-porous region and a porous region including a top porous layer (Porous Region 1) having a first thickness and a first porosity, and a bottom porous layer (Porous Region 2) located beneath the top porous layer and forming an interface with the non-porous region. At least an upper portion of the non-porous region and the entirety of the porous region are composed of silicon, and the bottom porous layer has a second thickness that is greater than the first thickness, and a second porosity that is greater than the first porosity.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.