Patents by Inventor John Alan Maxwell

John Alan Maxwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230281010
    Abstract: An application includes a runtime environment that is operable on a portable binary-code format. The application references a lens file that defines a binary lens compiled to the portable binary-code format from an arbitrary programming language. The lens file further defines parameters passable to the binary lens as arguments. The binary lens is executable with the application on data of a first schema to transform the data to a second schema. The lens file may compose binary lenses defined in lens modules. Lens modules and lens files may be distributed through a repository.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Inventor: John-Alan Maxwell SIMMONS
  • Publication number: 20210110105
    Abstract: Systems, devices, and methods for fileless information management are provided. A system includes a content-management server in communication with at least one client device via a computer network. The client device has a client user interface to concurrently display a content-editing area and a content card-management area. The content-management server stores content data and content card template metadata shareable between client devices. The content-management server stores programming instructions for a content card-management program for receiving, storing, and transmitting content data via content card templates. A content card template may include metadata associating content data stored in the memory with a content binding in the content-editing area of a client device.
    Type: Application
    Filed: March 4, 2019
    Publication date: April 15, 2021
    Inventors: Adnan SMAJIC, David Patrick TURNER, Alexandru Sebastian GOGAN, John-Alan Maxwell SIMMONS
  • Patent number: 7154174
    Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate. High interconnect densities are achieved through the use of a multilayer printed circuit board. This high interconnect density, with the addition of a magnetic core element, allows the power supply packaging system to incorporate transformer windings for an isolation transformer or an inductor.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: December 26, 2006
    Assignee: Power-One, Inc.
    Inventor: John Alan Maxwell
  • Patent number: 7027305
    Abstract: The invention provides arrangements to facilitate surface mounting of subassembly boards on a motherboard with reliable, high conductivity interconnection. In accordance with the invention, the subassembly interconnection arrangement is composed of separate power and sense connector arms formed on one or more base headers. The arrangement interconnects and supports the subassembly board on the motherboard surface. Each power arm advantageously comprises a plurality of split-based mounting lugs secured to the arm in a coplanar configuration. Each sense connector arm preferably comprises a plurality of connector pins secured to the arm in a coplanar configuration. Embodiments are disclosed for vertical and horizontal surface mounting.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: April 11, 2006
    Assignee: Power-One, Inc.
    Inventors: David Keating, Antoin Russell, Mysore P. Divakar, Thomas H. Templeton, John Alan Maxwell
  • Patent number: 6946744
    Abstract: A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: September 20, 2005
    Assignee: Power-One Limited
    Inventors: John Alan Maxwell, Mysore Purushotham Divakar, Thomas Henry Templeton, Jr.
  • Publication number: 20040212054
    Abstract: A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Applicant: Power-One Limited
    Inventors: John Alan Maxwell, Mysore Purushotham Divakar, Thomas Henry Templeton