Abstract: This invention furnishes a semiconductor shift register circuit characterized in that each stage of the register contains a dynamic "master" portion feeding a static "slave" portion. The register circuit is driven by a suitable clock voltage circuit such that if the signal source for the clock circuit should stop, then the information in each stage is retained and is stored in the static portion. In this way, the overall performance of the shift register is static in the sense that the information in the register is not lost during temporary stoppage of the driving clock; yet, fewer electrical component elements are required per entire stage than in the case of a fully static stage.

Abstract: A capacitor in parallel with a CMOS memory is used, in the event of a power outage, to apply a sufficient temporary voltage to the memory to maintain the stored data. Data storage retention time is maximized by a resistor, connected between the capacitor and the memory, having a resistance R approximately given byR = 0.4 (V.sub.i - V.sub.f)/I.sub.f (1)where V.sub.i is the initial voltage on the capacitor, V.sub.f is the minimum voltage for maintaining the data and I.sub.f is the capacitor discharge current at voltage V.sub.f.