Patents by Inventor John Apodaca

John Apodaca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134527
    Abstract: Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Michael Apodaca, Yoav Harel, Guei-Yuan Lueh, John A. Wiegert
  • Patent number: 11948017
    Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device; and a central processing unit (CPU). In some examples, the CPU is configured to: execute a producer to issue graphics command application program interfaces (APIs); execute a driver to translate graphics command APIs into executable instructions; and based on an idle state of the producer, execute a command translation code segment of the producer to translate graphics command APIs into executable instructions. In some examples, the execution unit is coupled to the memory device, the execution unit to execute one or more of the executable instructions. In some examples, the producer includes multiple portions such as application code, graphics pipeline runtime code, and command translation code segment.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek Venkatesh, Michael Apodaca, Stav Gurtovoy, John H. Feit, Mateusz Przybylski, David M. Cimini
  • Patent number: 5375313
    Abstract: A device for the removal of a liner bolt from a SAG mill including a support member for affixing to an exterior surface of the SAG mill and a ram affixed to the support member and having an end movable relative to the support member. The end serves for compressive abutment with a surface of a liner bolt. The support member includes a first arm, a second arm, and a strut connected to the first and second arms. The ram is affixed to the strut. A first bolt receptacle is formed on an end of the first arm and a second bolt receptacle is formed on an end of the second arm. The ram includes a cylindrical member affixed to and extending downwardly from the support member, a circular frame affixed to the support member and rigidly affixed to the cylindrical member, and a hydraulic ram having a body received within the cylindrical member.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: December 27, 1994
    Assignee: Battle Mountain Gold Company
    Inventors: John Apodaca, Mike Bohl, Moises Cordova, Denny Gonzales, Louie Lucero, Jesse Martinez, James Mascarenas, Leonard Quintana