Patents by Inventor John Atkinson Fifield
John Atkinson Fifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7688654Abstract: A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.Type: GrantFiled: June 28, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Darren Lane Anand, John Atkinson Fifield, Michael Richard Ouellette
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Publication number: 20090256591Abstract: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.Type: ApplicationFiled: April 15, 2008Publication date: October 15, 2009Inventors: John Atkinson Fifield, Michael Richard Ouellette
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Patent number: 7541834Abstract: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.Type: GrantFiled: May 15, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Michael Richard Ouellette
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Patent number: 7466582Abstract: A design structure comprising a static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WLO-WLN) and a voltage regulator (240, 240?, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.Type: GrantFiled: June 15, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Harold Pilo
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Publication number: 20080001251Abstract: A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.Type: ApplicationFiled: June 28, 2007Publication date: January 3, 2008Inventors: Darren Lane Anand, John Atkinson Fifield, Michael Richard Ouellette
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Patent number: 7276775Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.Type: GrantFiled: December 26, 2002Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Anthony J. Dally, John Atkinson Fifield, John Jesse Higgins, Jack Allan Mandelman, William Robert Tonti, Nicholas Martin van Heel
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Patent number: 7227239Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.Type: GrantFiled: September 23, 2004Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, John Atkinson Fifield, Robert J. Gauthier, Jr., William Robert Tonti
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Patent number: 7068105Abstract: A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.Type: GrantFiled: September 20, 2005Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Steven Harley Lamphier
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Patent number: 6975169Abstract: A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.Type: GrantFiled: January 21, 2004Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Steven Harley Lamphier
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Patent number: 6737907Abstract: A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.Type: GrantFiled: July 3, 2001Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Li-Kong Wang, John Atkinson Fifield, Wayne F. Ellis
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Publication number: 20030109090Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.Type: ApplicationFiled: December 26, 2002Publication date: June 12, 2003Applicant: International Business Machines CorporationInventors: Claude Louis Bertin, Anthony J. Dally, John Atkinson Fifield, John Jesse Higgins, Jack Allan Mandelman, William Robert Tonti, Nicholas Martin van Heel
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Patent number: 6577156Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.Type: GrantFiled: December 5, 2000Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: Darren L. Anand, John Edward Barth, Jr., John Atkinson Fifield, Pamela Sue Gillis, Peter O. Jakobsen, Douglas Wayne Kemerer, David E. Lackey, Steven Frederick Oakland, Michael Richard Ouellette, William Robert Tonti
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Patent number: 6570806Abstract: A universal fuse latch device includes a latch circuit receiving an electrical signal for initializing the latch circuit to a first state; one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state; and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate reading of one of the fuse and anti-fuse type elements. The universal fuse latch device may be part of a programmable fuse bank including a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is programmed in accordance with a priority of legs to be interrogated in the information fuse latches.Type: GrantFiled: June 25, 2001Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, John Atkinson Fifield, Nicholas Martin Van Heel, Jason Timothy Varricchione
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Publication number: 20030052729Abstract: A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.Type: ApplicationFiled: July 3, 2001Publication date: March 20, 2003Applicant: International Business Machines CorporationInventors: Louis L. Hsu, Li-Kong Wang, John Atkinson Fifield, Wayne F. Ellis
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Patent number: 6531410Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.Type: GrantFiled: February 27, 2001Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Anthony J. Dally, John Atkinson Fifield, John Jesse Higgins, Jack Allan Mandelman, William Robert Tonti, Nicholas Martin van Heel
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Patent number: 6522154Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method includes the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.Type: GrantFiled: March 16, 2001Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: John Atkinson Fifield, Mark David Jacunski, Thomas Martin Maffitt, Nicholas Van Heel
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Patent number: 6455778Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.Type: GrantFiled: June 28, 2001Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Thomas George Ference, Wayne John Howell, John Atkinson Fifield
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Publication number: 20020130672Abstract: A method of, and a circuit for, measuring a capacitor gate dielectric thickness. The method comprises the step of providing a circuit including a gate dielectric capacitor, and charging the circuit with a known current. A voltage output from said circuit is measured, and this voltage is proportional to the gate dielectric capacitor thickness. The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.Type: ApplicationFiled: March 16, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: John Atkinson Fifield, Mark David Jacunski, Thomas Martin Maffitt, Nicholas Van Heel
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Patent number: 6444490Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.Type: GrantFiled: June 28, 2001Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Thomas George Ference, Wayne John Howell, John Atkinson Fifield
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Publication number: 20020119637Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.Type: ApplicationFiled: February 27, 2001Publication date: August 29, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claude Louis Bertin, Anthony J. Dally, John Atkinson Fifield, John Jesse Higgins, Jack Allan Mandelman, William Robert Tonti, Nicholas Martin van Heel