Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Abstract: A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Abstract: Techniques and mechanisms for determining a write recovery time of a memory device. In an embodiment, thermal detection logic detects a signal from a thermal sensor indicating a temperature state of a resource of the memory device. A value of a write recovery parameter is set based on the signal from the thermal sensor. In another embodiment, command logic generates a signal to precharge one or more cells of the memory device. The write recovery parameter is used by timer logic to control a timing of the signal to precharge the one or more cells.

Abstract: A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract: Techniques and mechanisms for providing state information describing one or more data errors detected locally at a memory device. In an embodiment, the memory device includes a memory core and error detection circuit logic configured to detect for errors of data stored by the memory core. A die of the memory device includes both the memory core and the error detection circuitry. In another embodiment, state information is stored in a mode register of the memory device in response to the error detection logic detecting an occurrence of a data error. The state information is available for access by a memory controller or other agent which is external to the memory device.

Abstract: A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract: A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the count in response to detecting a command to activate the row. Circuitry of counter may further set a value of the count to a baseline value in response to detecting a command to refresh the row. In another embodiment, the memory device includes evaluation logic to compare a value of the count to a threshold value. A signal is generated based on the comparison to indicate whether a row hammer event for the row is indicated.

Abstract: A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

Abstract: A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.