Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and responsive to a determination that the memory request is not speculative, ensuring that a prefetch lock indicator of a cache line of a cache associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“CRA”) from flushing the associated cache line.

Abstract: System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a number of pending memory requests for the entity is less than a prefetch limit therefor; and responsive to a determination that the number of pending memory requests for the entity is less than the prefetch limit therefor, issuing a new memory request comprising a portion of the received DMA transaction.

Abstract: System and method of memory utilization in a computer system are described. In one embodiment, the method comprises storing a DMA transaction received from an entity in a request address first-in, first out buffer (“RAF”); determining whether a first DMA transaction stored in the RAF is a read request; and responsive to a determination that the first DMA transaction is a read request, issuing at least one prefetch memory request in connection with the read request; otherwise, forgoing issuance of at least one prefetch memory request in connection with the first DMA transaction and determining whether a next DMA transaction stored in the RAF is a read request.

Abstract: System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is equal to or less than a number of cache lines of a cache memory; and responsive to a determination that the number of pending requests is less than the fetch limit, performing an arbitration among all of the pending requests, including the new cache line-sized memory request.

Abstract: Disclosed are systems and methods providing a unified system fabric in a computer. The systems and methods of embodiments including first interface disposed between a first component of the computer system and a second component of the computer system, the first interface implementing an interface protocol, and a second interface disposed between the first component of the computer system and a third component of the computer system, the second interface implementing the interface protocol, wherein the first interface and the second interface comprise separate signal paths at the first component.

Abstract: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.