Abstract: An embodiment of the invention may include a circuit structure. The circuit structure may include a wiring tree located between a feeding Josephson transmission line (FJTL) and a global bias line. The circuit may include the wiring tree having an H-tree structure, wherein each branch of the H-tree is connected by a current limiting junction of the FJTL, and wherein a single output port of the H-tree structure is connected to the global bias line. Another embodiment of the invention may include a circuit structure a circuit structure a plurality of feeding Josephson transmission lines (FJTLs) located between a feed line and a global bias line. The path of from the feed line through each FJTL and to the global bias line is substantially similar.

Abstract: A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.