Abstract: A window having a window panel that slides in a frame and at least one balancer that is secured to the window panel is disclosed. The window is of the tiltable hung type having a vertical operating position in which the balancer slides with the window panel in the frame and a tilted position in which the balancer remains secured to the window panel. The balancer includes an extensible member having a first end operatively coupled to the balancer and a second end operatively coupled to a frame so that the balancer can exert a force on the window panel to assist against the force of gravity when the window panel is in the vertical operating position. A method of constructing a tiltable hung window with a balancer secured to the window panel is also disclosed.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: A window having a window panel that slides in a frame and at least one balancer that is secured to the window panel is disclosed. The window is of the tiltable hung type having a vertical operating position in which the balancer slides with the window panel in the frame and a tilted position in which the balancer remains secured to the window panel. The balancer includes an extensible member having a first end operatively coupled to the balancer and a second end operatively coupled to a frame so that the balancer can exert a force on the window panel to assist against the force of gravity when the window panel is in the vertical operating position. A method of constructing a tiltable hung window with a balancer secured to the window panel is also disclosed.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: A disposable absorbent article to be worn about the lower torso of a wearer that facilitates an easy, intuitive change is provided. The disposable absorbent article includes at least one serviceable indicium that facilitates an easy, intuitive change by aligning the article relative to an anatomical feature of the wearer or relative to a component of the article thereby enhancing the fit and corresponding performance of the article.

Abstract: A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowed. This includes logically combining and registering the unborrowed product terms. The macrocell may include circuitry for feeding back to the AND array of the programmable logic device a combinatorial or registered signal of the macrocell, and also outputting such a combinatorial or registered signal from the macrocell. When a combinatorial signal is fed back, the register of the macrocell can be used for another signal of the macrocell.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

Abstract: A system for generating voltages on an integrated circuit utilizes an overlapping clocking scheme. An oscillator generates the overlapping clock signals, which are coupled through oscillator buffers, to row pumps. In response to the overlapping clock signals, row pumps generate high voltages, typically higher than the VDD voltage of the integrated circuit. These high voltages may be used to program programmable memory cells or interface to logic components of the integrated circuit.

Abstract: An output buffer comprising control circuit for reducing the amount of ground and/or power bounce noise. The output buffer further includes one or more driver devices. The output current of the driver device(s) is limited by providing an intermediate drive voltage to the control electrode of the driver device. A pass device (or a transmission gate) provides the intermediate drive voltage and also operates as a variable resistive device that limits the slew rate of the drive voltage. The operation of the pass device can be dependent on a signal level at the output of the output buffer. When the output has transitioned to a new logic state, the new logic level is fed back to change the operating state of the pass device, thus ensuring that the output voltage meets the output VOL and VOH specifications.